公开(公告)号：US06666368B2

公开(公告)日：2003-12-23

申请号：US10016270

申请日：2001-11-02

Applicant: Glenn A. Rinne

Inventor： Glenn A. Rinne

IPC: B23K3102

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1319 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/81121 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K1/0212 ,  H05K3/3436 ,  H05K2201/10484 ,  H05K2203/0278 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A second substrate is positioned relative to a first substrate having phase-changeable bumps, such as solder bumps, between them, wherein the second substrate has a first face adjacent the first substrate, a second face remote from the first substrate, and at least one edge wall between the first and second faces. The phase-changeable bumps are liquefied to establish an equilibrium position of the first and second substrates relative to one another. At least a portion of the second face is pushed away from the equilibrium position towards the first substrate, to a new position, without applying external force to the first face other than spring forces of the phase-changeable bumps that are liquefied, and without applying external force to any edge wall. Thus, only spring forces of the phase-changeable bumps that are liquefied oppose the pushing. The phase-changeable bumps that are liquefied then are solidified, to maintain the new position.

公开(公告)号：US20020181214A1

公开(公告)日：2002-12-05

申请号：US09872122

申请日：2001-05-31

Inventor： Paul S. Levy ,  David Frame

IPC: H05K007/02

CPC classification number: H05K1/141 ,  H05K1/181 ,  H05K3/3447 ,  H05K2201/0792 ,  H05K2201/1034 ,  H05K2201/10484 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: A dual-sided circuit board module designed for an operating position that is not perpendicular to a system motherboard will be coupled to the motherboard by leads having at least two different lengths. Because leads of differing lengths have differing associated inductance, the operating characteristics of the leads and therefore the devices coupled to the leads will differ. In order to improve the operating characteristics of the module, integrated circuit packages are selected based on the inductive (and possibly other) qualities of the leads to which the respective packages are coupled. In one embodiment, leads having a larger inductance are coupled to integrated circuit (IC) packages having a smaller inductance and vice versa, which allows the inductive characteristics of the various components of the module to have more closely matching inductive characteristics than would otherwise be possible.

Abstract translation: 设计用于不垂直于系统主板的操作位置的双面电路板模块将通过具有至少两个不同长度的引线耦合到母板。 因为不同长度的引线具有不同的相关电感，所以引线的工作特性以及耦合到引线的器件的操作特性将不同。 为了提高模块的工作特性，集成电路封装是基于各个封装所耦合的引线的电感（也可能是其它）的质量来选择的。 在一个实施例中，具有较大电感的引线被耦合到具有较小电感的反馈的集成电路（IC）封装，这允许模块的各种部件的电感特性具有比否则可能更紧密匹配的感应特性 。

公开(公告)号：US20020171954A1

公开(公告)日：2002-11-21

申请号：US10105574

申请日：2002-03-25

Inventor： Timothy A. Bonardi ,  Frederick T. Bauer

IPC: F21S008/10

CPC classification number: H05K1/189 ,  B60Q1/2665 ,  B60R1/07 ,  B60R1/088 ,  B60R1/1207 ,  H05K1/02 ,  H05K1/18 ,  H05K3/0058 ,  H05K2201/09072 ,  H05K2201/09081 ,  H05K2201/10106 ,  H05K2201/10484

Abstract: A rearview mirror assembly of the present invention includes a circuit board disposed behind the mirror. The circuit board may be a flexible circuit board and may include an LED mounted to project light through a transparent window in the flexible circuit board and through the mirror. The flexible circuit board may function as a mirror heater and may include conductive paths for connection to the LED and/or electrodes of an electrochromic mirror. The LED may include an LED chip mounted directly on the circuit board and encapsulated thereon by an encapsulant.

Abstract translation: 本发明的后视镜组件包括设置在反射镜后面的电路板。 电路板可以是柔性电路板，并且可以包括安装成将光投射穿过柔性电路板中的透明窗口并通过反射镜的LED​​。 柔性电路板可以用作镜面加热器，并且可以包括用于连接到电致变色镜的LED​​和/或电极的导电路径。 LED可以包括直接安装在电路板上并通过密封剂封装在其上的LED芯片。

公开(公告)号：US20020170943A1

公开(公告)日：2002-11-21

申请号：US10152641

申请日：2002-05-21

Applicant: JDS Uniphase Corporation

Inventor： Philip Deane

IPC: B23K031/02

CPC classification number: H01L24/81 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12043 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2201/10484 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/00

Abstract: A method for solder bonding a photodiode or an array of photodiodes to a substrate, the photodiode(s) tilted at a predetermined angle, uses a pair solder bumps placed on a photodiode chip opposite a corresponding pair of asymmetric solder pads placed on the substrate. When the photodiode chip is placed on the substrate, with the solder bumps therebetween, the solder is melted and undergoes a reflow over the surface of the pads. This causes the chip to tilt to one side about the axis defined by the asymmetric pads.

Abstract translation: 将光电二极管或阵列的光电二极管焊接到基板上的方法，即以预定角度倾斜的光电二极管使用放置在与放置在基板上的对应的一对不对称焊盘相对的光电二极管芯片上的一对焊料凸块。 当光电二极管芯片放置在基板上时，焊料凸起之间，焊料熔化并在焊盘的表面上经过回流焊。 这使得芯片围绕由不对称焊盘限定的轴线倾斜到一侧。

公开(公告)号：US06420782B1

公开(公告)日：2002-07-16

申请号：US09478917

申请日：2000-01-06

Applicant: Kian Teng Eng ,  Lee Teck Yeow

Inventor： Kian Teng Eng ,  Lee Teck Yeow

IPC: H01L2302

CPC classification number: H01L24/06 ,  H01L23/057 ,  H01L23/49805 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/78252 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/10454 ,  H05K2201/10484 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An integrated circuit package (30, 32) for vertical attachment as part of a high density module (200) comprising a carrier (70) having an opening (86), routing strips (82), conduits (84) and side surface terminals (100), the side surface terminals (100) disposed on a side surface (92), which side surface is common to the carrier (70) and the integrated circuit package 30, 32. An adhesive layer (60), which attaches a silicon chip (50) to a carrier (70), wire bonding (80) electrically connecting the silicon chip (50) to the routing strips (82) and potting material (90) filling the opening (86), are also disclosed.

Abstract translation: 一种用于垂直附接作为高密度模块（200）的一部分的集成电路封装（30,32），包括具有开口（86）的载体（70），布线条（82），导管（84）和侧表面端子 100），设置在侧表面（92）上的侧表面端子（100），该侧表面与载体（70）和集成电路封装30,32共用。粘合剂层（60），其附着硅 还公开了将芯片（50）连接到载体（70），将硅芯片（50）电连接到布线条（82）的引线接合（80）和填充开口（86）的灌封材料（90）。

公开(公告)号：US20020086459A1

公开(公告)日：2002-07-04

申请号：US09908850

申请日：2001-07-20

Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA

Inventor： Takao Nakajima

IPC: H01L021/00 ,  H01L021/44 ,  H01L021/48 ,  H01L021/50 ,  H01L023/02 ,  H01L029/40

CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/144 ,  H05K1/183 ,  H05K3/3436 ,  H05K2201/049 ,  H05K2201/10189 ,  H05K2201/10484 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: This invention provides a circuit mounting method and a circuit mounted board which can mount semiconductor elements at a high density. A recessed portion is formed in a board, a memory IC packaged in a chip size package method (CSP) is mounted in the recessed portion, and a memory IC packaged in a thin small outline package method (TSOP) is mounted on the board to cover the recessed portion.

Abstract translation: 本发明提供一种可以高密度安装半导体元件的电路安装方法和电路安装板。 在基板上形成有凹部，在凹部中安装以芯片尺寸封装方法（CSP）封装的存储器IC，将封装成薄型小型封装方法（TSOP）的存储IC安装在板上， 覆盖凹陷部分。

公开(公告)号：US06377468B1

公开(公告)日：2002-04-23

申请号：US09593862

申请日：2000-06-15

Applicant: Hideyuki Ohtani ,  Fukuo Ishikawa ,  Hideki Kabune ,  Hiroshi Hattori

Inventor： Hideyuki Ohtani ,  Fukuo Ishikawa ,  Hideki Kabune ,  Hiroshi Hattori

IPC: H05K702

CPC classification number: H05K1/0201 ,  H05K1/141 ,  H05K3/341 ,  H05K2201/10166 ,  H05K2201/10181 ,  H05K2201/10484 ,  H05K2203/159 ,  H05K2203/176 ,  Y10T29/49144

Abstract: Circuit elements of surface-mounting type such as MOSFETs etc. are mounted on a circuit board by soldering. The circuit board is retained slantingly by a base so that any one of the MOSFET falls out by its self-weight when the solder melts due to an abnormal heat generation of the MOSFET. The falling of the MOSFET is stopped by a stopper member, and then the MOSFET becomes in an electrically open state and retained at the stopped position in consequence of the subsequent cooling of the solder. Accordingly, even if one or more of the MOSFETs cause the abnormal heat generation, the continuous heat generation of the MOSFET is stopped and also the other circuit elements are prevented from being short-circuited.

Abstract translation: 诸如MOSFET等的表面安装型电路元件通过焊接安装在电路板上。 电路板由基座倾斜地保持，使得当焊料由于MOSFET的异常发热而熔化时，MOSFET中的任何一个通过其自重而下降。 MOSFET的下降通过止动件停止，然后由于随后的焊料冷却，MOSFET变成电打开状态并保持在停止位置。 因此，即使一个或多个MOSFET引起异常发热，MOSFET的连续发热也停止，并且防止其它电路元件短路。

公开(公告)号：US06375365B1

公开(公告)日：2002-04-23

申请号：US09514424

申请日：2000-02-28

Applicant: Kelvin Chau

Inventor： Kelvin Chau

IPC: G02B636

CPC classification number: G02B6/43 ,  G02B6/422 ,  G02B6/4231 ,  H05K3/303 ,  H05K3/305 ,  H05K3/3447 ,  H05K2201/10303 ,  H05K2201/10318 ,  H05K2201/10484 ,  Y02P70/613

Abstract: For any optically interconnected assembly, the packaging tasks include alignment of one or multiple optical devices, and attachment of aligned modules to a common substrate. The concept disclosed here is a packaging method to assemble pre-aligned optical modules on a common structure called motherboard. The apparatus consists of two components: device carrier or motherboard with openings on the sides and adjustable plugs in the form of pins or balls. The method and apparatus utilize plugs as connection bridges between device carriers and motherboard, allowing solid contacts and a rigid aligned structure among modules. The direct benefits include relaxation of dimensional tolerances on parts and elimination of the need for high-precision spacers.

Abstract translation: 对于任何光学互连组件，包装任务包括一个或多个光学装置的对准，以及将对准的模块附接到公共衬底。 这里公开的概念是将预对准的光学模块组装在称为母板的公共结构上的封装方法。 该设备由两部分组成：设备载体或主板，侧面有开口，可调节插头为销或球形。 该方法和装置利用插头作为装置载体和母板之间的连接桥，允许模块之间的固体触点和刚性对准结构。 直接的优点包括放宽零件的尺寸公差，消除对高精度垫片的需求。

公开(公告)号：US06320126B1

公开(公告)日：2001-11-20

申请号：US09115565

申请日：1998-07-14

Applicant: Kian Teng Eng ,  Lee Teck Yeow

Inventor： Kian Teng Eng ,  Lee Teck Yeow

IPC: H01L2328

CPC classification number: H01L24/06 ,  H01L23/057 ,  H01L23/49805 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/78252 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/10454 ,  H05K2201/10484 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An integrated circuit package (30, 32) for vertical attachment as part of a high density module (200) having a carrier (70) having an opening (86), routing strips (82), conduits (84) and side surface terminals (100), the side surface terminals (100) disposed on a side surface (92), which side surface is common to the carrier (70) and the integrated circuit package 30, 32. An adhesive layer (60), which attaches a silicon chip (50) to a carrier (70), wire bonding (80) electrically connecting the silicon chip (50) to the routing strips (82) and potting material (90) filling the opening (86), are also disclosed.

Abstract translation: 一种用于垂直附接的集成电路封装（30,32），作为具有开口（86）的载体（70）的高密度模块（200）的一部分，布线条（82），导管（84）和侧表面端子 100），设置在侧表面（92）上的侧表面端子（100），该侧表面与载体（70）和集成电路封装30,32共用。粘合剂层（60），其附着硅 还公开了将芯片（50）连接到载体（70），将硅芯片（50）电连接到布线条（82）的引线接合（80）和填充开口（86）的灌封材料（90）。

公开(公告)号：US06191493B1

公开(公告)日：2001-02-20

申请号：US09260594

申请日：1999-03-02

Applicant: Masatoshi Yasunaga ,  Shin Nakao ,  Shinji Baba ,  Mitsuyasu Matsuo ,  Hironori Matsushima

Inventor： Masatoshi Yasunaga ,  Shin Nakao ,  Shinji Baba ,  Mitsuyasu Matsuo ,  Hironori Matsushima

IPC: H01L2144

CPC classification number: H01L21/568 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L25/10 ,  H01L25/105 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1191 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4813 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2225/1005 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K3/303 ,  H05K3/3442 ,  H05K2201/09909 ,  H05K2201/10454 ,  H05K2201/10484 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.

Abstract translation: 接合焊盘形成在半导体芯片的主表面上。 在半导体芯片的主表面上形成具有位于接合焊盘上的开口的绝缘层。 在接合焊盘上形成基底金属层。 在绝缘层上形成具有放置在基底金属层周围的部分的缓冲涂膜。 连接层形成在基底金属层上。 第一导体形成在连接层上。 形成仅露出第一导体的顶表面的密封树脂。 在第一导体的顶表面上形成笨重的第二导体。 因此，可以使树脂密封半导体封装紧凑并且具有改善的电特性和高可靠性。