公开(公告)号：US06603321B2

公开(公告)日：2003-08-05

申请号：US09999719

申请日：2001-10-26

Applicant: Ronald G. Filippi, Jr. ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Deborah Tibel ,  Michael Ruprecht ,  Carole Graas

Inventor： Ronald G. Filippi, Jr. ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Deborah Tibel ,  Michael Ruprecht ,  Carole Graas

IPC: G01R3126

CPC classification number: H01L22/34 ,  G01R31/2858 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method for determining the electromigration characteristics of a wiring structure in an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes configuring a defined test structure type for the integrated circuit device. The defined test structure type further includes a first line of wiring primarily disposed in a principal plane of a semiconductor substrate, and a second line of wiring connected to the first line of wiring. The second line of wiring is disposed in a secondary plane which is substantially parallel to the principal plane, with the first and second lines of wiring being connected by a via structure therebetween. A thermal coefficient of resistance for the first line of wiring and the via structure is determined, and a wafer-level stress condition is introduced in a first individual test structure of the defined test structure type. Then, at least one parameter value for is determined for the first individual test structure, which parameter value is used to predict a lifetime projection for the wiring structure in the integrated circuit device.

Abstract translation: 公开了一种用于确定集成电路器件中的布线结构的电迁移特性的方法。 在本发明的示例性实施例中，该方法包括配置用于集成电路器件的定义的测试结构类型。 所确定的测试结构类型还包括主要布置在半导体衬底的主平面中的第一布线和连接到第一布线的第二布线。 布线的第二线设置在基本上平行于主平面的二次平面中，其中第一和第二布线通过它们之间的通孔结构连接。 确定第一线路和通孔结构的电阻的热系数，并且在限定的测试结构类型的第一单独测试结构中引入晶片级应力条件。 然后，对于第一单独测试结构确定至少一个参数值，哪个参数值用于预测集成电路器件中的布线结构的寿命投影。

公开(公告)号：US5233263A

公开(公告)日：1993-08-03

申请号：US722768

申请日：1991-06-27

Applicant: John E. Cronin ,  Kent E. Morrett ,  Michael D. Potter ,  Timothy D. Sullivan

Inventor： John E. Cronin ,  Kent E. Morrett ,  Michael D. Potter ,  Timothy D. Sullivan

IPC: H01J1/304 ,  H01J9/02

CPC classification number: H01J9/025 ,  H01J1/3042

Abstract: Lateral cathode field emission devices and methods of fabrication are set forth. Conventional integrated circuit fabrication techniques are advantageously used to produce the lateral FEDs. Cathode tips on the order of several hundred angstroms are consistently obtained as well as exact spacing of the cathode to gate and cathode to anode. Various cathode and device configurations are described, including a circular field emission device. A single integrated structure having multiple cathodes and multiple gates is possible to perform various logic operations and/or enhance current output from the device. Multiple field effect devices, with cathodes disposed parallel or perpendicular to the substrate, are integrally coupled through a sharing of one or more metallization layers definitive of the elements of the devices. Significant advantages in current density and circuit layout can be obtained. Methods for fabricating the various devices are also explained.

Abstract translation: 阐述了侧向阴极场发射器件及其制造方法。 传统的集成电路制造技术有利地用于产生横向FED。 一贯获得数百埃数量级的阴极尖端，以及阴极与栅极和阴极与阳极的精确间距。 描述了各种阴极和器件配置，包括圆形场致发射器件。 具有多个阴极和多个栅极的单个集成结构可以执行各种逻辑操作和/或增强来自该器件的电流输出。 具有平行或垂直于衬底设置的阴极的多个场效应器件通过共享设备元件的一个或多个金属化层而被一体地耦合。 可以获得电流密度和电路布局的显着优点。 还说明了制造各种装置的方法。

公开(公告)号：US09607862B2

公开(公告)日：2017-03-28

申请号：US13610262

申请日：2012-09-11

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L21/306 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05113 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05613 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/014

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4 bump and contacting a side of the C4 bump. The method can further include recessing a portion of the PSPI layer adjacent to the C4 bump to form a PSPI pedestal under the C4 bump. The method can additionally include forming an underfill abutting the PSPI pedestal and the C4 bump, wherein the underfill and the solder form an interface separated from the PSPI pedestal.

公开(公告)号：US08922022B2

公开(公告)日：2014-12-30

申请号：US13356013

申请日：2012-01-23

Applicant: Baozhen Li ,  Paul S. McLaughlin ,  Timothy D. Sullivan

Inventor： Baozhen Li ,  Paul S. McLaughlin ,  Timothy D. Sullivan

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.

Abstract translation: 在导电通孔的上金属衬套和下面的金属线的下金属衬垫之间形成衬管到衬垫直接接触。 衬套到衬垫接触件阻止突然的电迁移故障并增强金属互连结构的电迁移阻力。 所述至少一个电介质材料部分可以包括多个电介质材料部分，其布置成确保上金属衬垫和下金属衬垫之间的直接接触。 或者，所述至少一个介电材料部分可以包括单个电介质部分，其中该区域具有与导电通孔的面积的足够的横向重叠，以确保在允许的光刻的范围内形成衬管到衬垫的直接接触 重叠变化。

公开(公告)号：US08803317B2

公开(公告)日：2014-08-12

申请号：US13433974

申请日：2012-03-29

Applicant: Charles L. Arvin ,  Raschid J. Bezama ,  Harry D. Cox ,  Timothy H. Daubenspeck ,  Krystyna W. Semkow ,  Timothy D. Sullivan

Inventor： Charles L. Arvin ,  Raschid J. Bezama ,  Harry D. Cox ,  Timothy H. Daubenspeck ,  Krystyna W. Semkow ,  Timothy D. Sullivan

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44 ,  H01L23/00

CPC classification number: H01L24/05 ,  C25D5/02 ,  C25D5/14 ,  C25D5/48 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05075 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/013 ,  H01L2924/01027

Abstract: Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying capabilities (e.g., current spreading). The structure includes an under bump metallurgy formed in a trench. The under bump metallurgy includes at least: an adhesion layer; a plated barrier layer; and a plated conductive metal layer provided between the adhesion layer and the plated barrier layer. The structure further includes a solder bump formed on the under bump metallurgy.

Abstract translation: 提供互连结构及其制造方法。 互连结构提供用于改善载流能力（例如，电流扩展）的高可靠性铜互连结构。 该结构包括在沟槽中形成的凸块下金属。 凸起下冶金至少包括：粘合层; 电镀阻挡层; 以及设置在粘合层和镀层阻挡层之间的镀覆导电金属层。 该结构还包括形成在凸块下金属上的焊料凸块。

公开(公告)号：US20140070401A1

公开(公告)日：2014-03-13

申请号：US13610262

申请日：2012-09-11

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L21/306 ,  H01L23/498

CPC classification number: H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05113 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05613 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/014

Abstract: Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4 bump and contacting a side of the C4 bump. The method can further include recessing a portion of the PSPI layer adjacent to the C4 bump to form a PSPI pedestal under the C4 bump. The method can additionally include forming an underfill abutting the PSPI pedestal and the C4 bump, wherein the underfill and the solder form an interface separated from the PSPI pedestal.

Abstract translation: 各种实施方案包括形成互连结构的方法以及通过这些方法形成的结构。 在一个实施例中，一种方法可以包括：提供具有：光敏聚酰亚胺（PSPI）层的前体互连结构; 一个控制崩溃芯片连接（C4）凸起覆盖PSPI层; 以及覆盖C4凸块并且接触C4凸块的一侧的焊料。 该方法还可以包括使与C4凸起相邻的PSPI层的一部分凹陷以在C4凸起下形成PSPI基座。 该方法还可以包括形成邻接PSPI基座和C4凸块的底部填充物，其中底部填充物和焊料形成与PSPI基座分离的界面。

公开(公告)号：US08637392B2

公开(公告)日：2014-01-28

申请号：US12700863

申请日：2010-02-05

Applicant: Charles L. Arvin ,  Raschid J. Bezama ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter ,  Timothy D. Sullivan ,  Brian R. Sundlof

Inventor： Charles L. Arvin ,  Raschid J. Bezama ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter ,  Timothy D. Sullivan ,  Brian R. Sundlof

IPC: H01L21/44

CPC classification number: H01L24/13 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/119 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01024 ,  H01L2924/01026 ,  H01L2924/01032 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.

Abstract translation: 焊接互连结构设置有不可润湿的侧壁及其制造方法。 该方法包括在下面的表面上形成镍或镍合金支柱。 该方法还包括修改镍或镍合金柱的侧壁以防止在侧壁上的焊料润湿。

公开(公告)号：US08629557B2

公开(公告)日：2014-01-14

申请号：US13414877

申请日：2012-03-08

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/48 ,  H01L21/00 ,  B23K31/00

CPC classification number: H01L22/30 ,  H01L22/12 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05584 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13028 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: Structures and methods for detecting solder wetting of pedestal sidewalls. The structure includes a semiconductor wafer having an array of integrated circuit chips, each of the integrated circuit chips having an array of chip pedestals having respective chip solder columns on top of the chip pedestals, the pedestals spaced apart a first distance in a first direction and a spaced apart second distance in second direction perpendicular to the first direction; and at least one monitor structure disposed in different regions of the wafer from the integrated circuit chips, the monitor structure comprising at least a first pedestal and a first solder column on a top surface of the first pedestal and a second pedestal and a second solder column on a top surface of the second pedestal, the first and the second pedestals spaced apart a third distance, the third distance less than the first and the second distances.

Abstract translation: 用于检测基座侧壁焊料润湿的结构和方法。 该结构包括具有集成电路芯片阵列的半导体晶片，每个集成电路芯片具有芯片基座阵列，其具有位于芯片基座顶部的相应的芯片焊料柱，基座沿第一方向隔开第一距离;以及 在垂直于第一方向的第二方向上间隔开的第二距离; 以及设置在所述晶片与所述集成电路芯片的不同区域中的至少一个监视器结构，所述监视器结构至少包括在所述第一基座的顶表面上的第一基座和第一焊料柱，以及第二基座和第二焊接柱 在第二基座的顶表面上，第一和第二基座间隔第三距离，第三距离小于第一和第二距离。

公开(公告)号：US20130234316A1

公开(公告)日：2013-09-12

申请号：US13415902

申请日：2012-03-09

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/05 ,  H01L21/31144 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/02375 ,  H01L2224/034 ,  H01L2224/03622 ,  H01L2224/0381 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/14104 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012

Abstract: The invention provides a semiconductor chip structure having at least one aluminum pad structure and a polyimide buffering layer under the aluminum pad structure, wherein the polyimide buffering layer is self-aligned to the aluminum pad structure, and a method of forming the same. The method includes forming a polyimide buffering layer on a substrate, forming an aluminum pad structure on the buffering layer, and, using the aluminum pad structure as a mask, etching the substrate to remove the polyimide buffering layer from the substrate everywhere except under the aluminum pad structure.

Abstract translation: 本发明提供一种半导体芯片结构，其具有在铝焊盘结构下方的至少一个铝焊盘结构和聚酰亚胺缓冲层，其中聚酰亚胺缓冲层与铝焊盘结构自对准，以及其形成方法。 该方法包括在基板上形成聚酰亚胺缓冲层，在缓冲层上形成铝焊盘结构，并且使用铝焊盘结构作为掩模，蚀刻基板以除去铝以外的其他处理的基板 垫结构。

公开(公告)号：US08426247B2

公开(公告)日：2013-04-23

申请号：US13463855

申请日：2012-05-04

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L21/44

CPC classification number: H01L23/49816 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/11822 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16 ,  H01L2224/17051 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10674 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A method of connecting chips to chip carriers, ceramic packages, etc. (package substrates) forms smaller than usual first solder balls and polymer pillars on the surface of a semiconductor chip and applies adhesive to the distal ends of the polymer pillars. The method also forms second solder balls, which are similar in size to the first solder balls, on the corresponding surface of the package substrate to which the chip will be attached. Then, the method positions the surface of the semiconductor chip next to the corresponding surface of the package substrate. The adhesive bonds the distal ends of the polymer pillars to the corresponding surface of the package substrate. The method heats the first solder balls and the second solder balls to join the first solder balls and the second solder balls into solder pillars.

Abstract translation: 将芯片与芯片载体，陶瓷封装等（封装基板）连接的方法比半导体芯片表面上的通常的第一焊球和聚合物柱形成的小，并且将粘合剂施加到聚合物柱的远端。 该方法还形成与芯片将附接到的封装衬底的相应表面上尺寸相似的第二焊球。 然后，该方法将半导体芯片的表面定位在封装衬底的相应表面的旁边。 粘合剂将聚合物柱的末端粘合到包装基底的相应表面上。 该方法加热第一焊球和第二焊球以将第一焊球和第二焊球接合成焊料柱。