公开(公告)号：US20080244902A1

公开(公告)日：2008-10-09

申请号：US11783306

申请日：2007-04-09

申请人： Kim J. Blackwell ,  Frank D. Egitto ,  John M. Lauffer ,  Voya R. Markovich

发明人： Kim J. Blackwell ,  Frank D. Egitto ,  John M. Lauffer ,  Voya R. Markovich

IPC分类号： H05K3/00

CPC分类号： H05K1/186 ,  H01L23/4985 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/4611 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/10515 ,  H05K2201/10681 ,  Y10T29/49126 ,  Y10T29/49151 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/0401

摘要： A circuitized substrate assembly comprised of at least two circuitized substrates each including a thin dielectric layer and a conductive layer with a plurality of conductive members as part thereof, the conductive members of each substrate being electrically coupled to the conductive sites of a semiconductor chip. A dielectric layer is positioned between both substrates and the substrates are bonded together, such that the chips are internally located within the assembly and oriented in a stacked orientation. A method of making such an assembly is also provided, as is an electrical assembly utilizing same and an information handling system adapted for having such an electrical assembly as part thereof.

摘要翻译： 电路化衬底组件由至少两个电路化衬底组成，每个衬底均包括薄介电层和具有多个导电构件作为其一部分的导电层，每个衬底的导电构件电耦合到半导体芯片的导电部位。 电介质层位于两个基板之间，并且基板接合在一起，使得芯片在内部位于组件内并且以堆叠取向定向。 还提供了制造这种组件的方法，以及使用其的电组件以及适于将这种电组件作为其一部分的信息处理系统。

公开(公告)号：US07384856B2

公开(公告)日：2008-06-10

申请号：US11172794

申请日：2005-07-05

申请人： Rabindra N. Das ,  John M. Lauffer ,  Voya R. Markovich ,  James T. Matthews

发明人： Rabindra N. Das ,  John M. Lauffer ,  Voya R. Markovich ,  James T. Matthews

IPC分类号： H01L21/20

CPC分类号： H05K1/162 ,  H05K3/4611 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2203/0207

摘要： A method of forming a capacitive substrate in which first and second conductors are formed opposite a dielectric, with one of these electrically coupled to a thru-hole connection. Each functions as an electrode for the resulting capacitor. The substrate is then adapted for being incorporated within a larger structure to form a circuitized substrate such as a printed circuit board or a chip carrier. Additional capacitors are also possible.

摘要翻译： 一种形成电容基板的方法，其中第一和第二导体与电介质相对地形成，其中一个电气基板电耦合到通孔连接。 每个都用作所得电容器的电极。 然后将衬底适用于并入更大的结构中以形成诸如印刷电路板或芯片载体的电路化衬底。 附加的电容器也是可能的。

公开(公告)号：US07348677B2

公开(公告)日：2008-03-25

申请号：US11397713

申请日：2006-04-05

申请人： James M. Larnerd ,  John M. Lauffer ,  Voya R. Markovich ,  Kostas I. Papathomas

发明人： James M. Larnerd ,  John M. Lauffer ,  Voya R. Markovich ,  Kostas I. Papathomas

IPC分类号： H01L29/40

CPC分类号： H05K3/429 ,  H01L2224/13 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/421 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/09845

摘要： A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by the other hole. It is also possible to connect all three conductive layers using one or more holes. The resulting holes may be filled, e.g., with metal plating, or conductive or non-conductive paste. In the case of the latter, it is also possible to provide a top covering conductive layer over the paste, e.g., to serve as a pad or the like on the board's external surface.

摘要翻译： 一种制造印刷电路板的方法，其中导电通孔形成在板结构的两个电介质层内，以便连接指定的导电层。 一个孔连接两个相邻的层，另一个连接两个相邻的层，包括通过另一个孔连接的一个导电层。 也可以使用一个或多个孔连接所有三个导电层。 所得到的孔可以例如用金属电镀或导电或不导电的糊料填充。 在后者的情况下，也可以在浆料上方设置顶部覆盖导电层，例如在板的外表面上用作衬垫等。

公开(公告)号：US07343674B2

公开(公告)日：2008-03-18

申请号：US11349998

申请日：2006-02-09

申请人： James W. Fuller, Jr. ,  John M. Lauffer ,  Voya R. Markovich

发明人： James W. Fuller, Jr. ,  John M. Lauffer ,  Voya R. Markovich

IPC分类号： H05K3/36 ,  H05K3/10 ,  H05K3/02

CPC分类号： H05K3/462 ,  H05K3/321 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167

摘要： A method of making a circuitized substrate assembly wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, and a cover is placed over one of the openings and a quantity of conductive paste is positioned thereon prior to bonding the substrates. At least some of the paste is then forced up into an opening in the other substrate as a result of the bonding.

摘要翻译： 一种制造电路化基板组件的方法，其中所述组件包括结合在一起的各个电路化基板。 基板各自包括至少一个开口，并且在其上面的一个开口上放置盖子，并且在粘合基板之前将一定数量的导电浆料放置在其上。 因此，粘合剂的至少一部分然后被迫上升到另一个基底中的开口中。

公开(公告)号：US07235745B2

公开(公告)日：2007-06-26

申请号：US11172786

申请日：2005-07-05

申请人： Rabindra N. Das ,  John M. Lauffer ,  Voya R. Markovich

发明人： Rabindra N. Das ,  John M. Lauffer ,  Voya R. Markovich

IPC分类号： H05K1/16

CPC分类号： H05K1/167 ,  H01G4/206 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/095 ,  H05K1/162 ,  H05K3/0023 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0215 ,  H05K2201/0257 ,  H05K2203/1453 ,  Y10T29/49082 ,  Y10T29/49087 ,  Y10T29/49089 ,  Y10T29/49091 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

摘要： A material for use as part of an internal resistor within a circuitized substrate includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. A circuitized substrate adapted for using such a material and resistor therein and a method of making such a substrate are also provided. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) are also provided.

摘要翻译： 用作电路化衬底内的内部电阻器的一部分的材料包括聚合物树脂和一定量的纳米粉末，其包括至少一种金属组分和至少一种陶瓷组分的混合物。 陶瓷部件可以是铁电陶瓷和/或高表面积陶瓷和/或透明氧化物和/或掺杂亚锰酸盐。 或者，材料将包括聚合物树脂和纳米粉末，其中纳米粉末包含至少一种金属涂覆的陶瓷和/或至少一种氧化物涂覆的金属组分。 还提供了适于在其中使用这种材料和电阻器的电路化基板和制造这种基板的方法。 还提供电气组件（基板和至少一个电气部件）和信息处理系统（例如，个人计算机）。

公开(公告)号：US07047630B2

公开(公告)日：2006-05-23

申请号：US10811915

申请日：2004-03-30

申请人： James W. Fuller, Jr. ,  John M. Lauffer ,  Voya R. Markovich

发明人： James W. Fuller, Jr. ,  John M. Lauffer ,  Voya R. Markovich

IPC分类号： H05K3/36

CPC分类号： H05K3/462 ,  H05K3/321 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167

摘要： A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.

摘要翻译： 电路化基板组件及其制造方法，其中所述组件包括结合在一起的各个电路化基板。 基板各自包括至少一个开口，其中仅一个开口在接合之前基本上填充有导电浆料。 一旦粘合，糊料也部分地位于另一个开口内，以提供与其的有效电连接。

公开(公告)号：US07025607B1

公开(公告)日：2006-04-11

申请号：US11031074

申请日：2005-01-10

申请人： Rabindra N. Das ,  John M. Lauffer ,  Voya R. Markovich ,  Mark D. Poliks

发明人： Rabindra N. Das ,  John M. Lauffer ,  Voya R. Markovich ,  Mark D. Poliks

IPC分类号： H01R4/58

CPC分类号： H01G4/206 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/162 ,  H05K3/0023 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0215 ,  H05K2201/0257 ,  H01L2224/0401

摘要： A material for use as part of an internal capacitor within a circuitized substrate includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ferroelectric ceramic component, the ferroelectric ceramic component nano-particles having a particle size substantially in the range of between about 0.01 microns and about 0.9 microns and a surface within the range of from about 2.0 to about 20 square meters per gram. A circuitized substrate adapted for using such a material and capacitor therein and a method of making such a substrate are also provided. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) are also provided.

摘要翻译： 用作电路化基板内的内部电容器的一部分的材料包括聚合物树脂和一定数量的纳米粉末，其包括至少一种金属组分和至少一种铁电陶瓷组分的混合物，所述铁电陶瓷组分纳米颗粒具有 基本上在约0.01微米至约0.9微米范围内的粒度和约2.0至约20平方米每克的表面。 还提供了适于在其中使用这种材料和电容器的电路化基板和制造这种基板的方法。 还提供电气组件（基板和至少一个电气部件）和信息处理系统（例如，个人计算机）。

公开(公告)号：US06986198B2

公开(公告)日：2006-01-17

申请号：US10744142

申请日：2003-12-22

申请人： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

发明人： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

IPC分类号： H05K3/36

CPC分类号： H05K3/445 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/056 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/0052 ,  H05K3/0094 ,  H05K3/06 ,  H05K3/108 ,  H05K3/426 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0919 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/10734 ,  H05K2203/0323 ,  H05K2203/0574 ,  H05K2203/0733 ,  H05K2203/1394 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method of forming a printed circuit card with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the card including a metal layer termination in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.

摘要翻译： 提供了一种在两个可光成像的电介质层之间形成具有金属功率平面层的印刷电路卡的方法。 通过孔穿过的光刻金属填充通孔位于光图案化材料中，信号电路位于连接到通孔和电镀通孔的每个介电材料的表面上。 边框可以在卡周围，包括从电介质层之一的边缘终止的金属层。 提供带有间隙孔的铜箔。 第一层和第二层可光成像的可固化电介质材料位于铜的相对两侧。 在可光成像材料的第一层和第二层上形成图案以通过通孔显露金属层。 开发了通孔，在两个电介质层中对其进行图案化。 可光成像材料，通孔和通孔的表面通过镀铜进行金属化，优选使用光致抗蚀剂。

公开(公告)号：US06832436B2

公开(公告)日：2004-12-21

申请号：US10094025

申请日：2002-03-07

申请人： Donald O. Anstrom ,  Bruce J. Chamberlin ,  James W. Fuller, Jr. ,  John M. Lauffer ,  Voya R. Markovich ,  Douglas O. Powell ,  Joseph P. Resavy ,  James R. Stack

发明人： Donald O. Anstrom ,  Bruce J. Chamberlin ,  James W. Fuller, Jr. ,  John M. Lauffer ,  Voya R. Markovich ,  Douglas O. Powell ,  Joseph P. Resavy ,  James R. Stack

IPC分类号： H01K310

CPC分类号： H01L23/50 ,  H01L23/5383 ,  H01L23/5385 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/3025 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09536 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

摘要： A method for forming a substructure or an electrical structure. To form the substructure, a sheet of conductive material having exposed first and second surfaces is provided. A hole is formed through the sheet of conductive material. A first layer of dielectric material is applied to the exposed first surface, after the forming the hole. No material was inserted into the hole before applying the first layer of dielectric material to the exposed first surface. To form the electrical structure, a multilayered laminate that includes a plurality of substructures is formed such that a dielectric layer insulatively separates each pair of successive substructures.

摘要翻译： 一种形成子结构或电结构的方法。 为了形成子结构，提供具有暴露的第一和第二表面的导电材料片。 通过导电材料片形成孔。 在形成孔之后，将第一层介电材料施加到暴露的第一表面。 在将第一层介电材料施加到暴露的第一表面之前，没有将材料插入孔中。 为了形成电气结构，形成包括多个子结构的多层层压体，使得介电层绝对地分离每对连续的子结构。

公开(公告)号：US06740819B2

公开(公告)日：2004-05-25

申请号：US10421272

申请日：2003-04-23

申请人： Anilkumar C. Bhatt ,  Ashwinkumar C. Bhatt ,  Subahu D. Desai ,  John M. Lauffer ,  Voya R. Markovich ,  Thomas R. Miller

发明人： Anilkumar C. Bhatt ,  Ashwinkumar C. Bhatt ,  Subahu D. Desai ,  John M. Lauffer ,  Voya R. Markovich ,  Thomas R. Miller

IPC分类号： H05K706

CPC分类号： H05K3/445 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0082 ,  H05K3/4641 ,  H05K2203/143

摘要： Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

摘要翻译： 通孔形成在导电电力平面中。 可光成像电介质（PID）材料被施加到填充通孔的电源平面的一侧。 没有PID材料的电源平面侧暴露于光能以固化通孔中的PID材料。 开发人员用于去除任何未固化的PID材料。 包括导电信号平面和电介质层的信号平面组件层压到形成两个信号和一个功率平面（2S1P）结构的填充的电源平面上。 在另一实施例中，动力平面具有从两侧施加的PID材料。 将光掩模应用于电源平面，通孔中的PID材料用光能固化。 开发人员用于清除未固化的PID材料。 如上所述的信号平面组件被层压到形成2S1P结构的填充的电源平面上。