公开(公告)号：US20130087951A1

公开(公告)日：2013-04-11

申请号：US13270957

申请日：2011-10-11

Applicant: Jing-Cheng Lin ,  Hsien-Wen Liu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Hsien-Wen Liu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H05B6/64 ,  B29C35/08

CPC classification number: B29C35/0805 ,  B29C2035/0855 ,  H01L21/565 ,  H05B6/6491 ,  H05B6/806

Abstract: An embodiment is a molding chamber. The molding chamber comprises a mold-conforming chase, a substrate-base chase, a first radiation permissive component, and a microwave generator coupled to a first waveguide. The mold-conforming chase is over the substrate-base chase, and the mold-conforming chase is moveable in relation to the substrate-base chase. The first radiation permissive component is in one of the mold-conforming chase or the substrate-base chase. The microwave generator and the first waveguide are together operable to direct microwave radiation through the first radiation permissive component.

公开(公告)号：US20130077272A1

公开(公告)日：2013-03-28

申请号：US13247659

申请日：2011-09-28

Applicant: Jing-Cheng Lin ,  Po-Hao Tsai

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H05K7/02 ,  H05K1/09

CPC classification number: H01L22/32 ,  H01L23/3192 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/13566 ,  H01L2224/13578 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/1369 ,  H01L2224/16148 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A work piece includes a first copper-containing pillar having a top surface and sidewalls, and a first protection layer on the sidewalls, and not over the top surface, of the first copper-containing pillar. A test pad includes a second copper-containing pillar having a top surface and sidewalls. The test pad is electrically coupled to the first copper-containing pillar. A second protection layer is disposed on the sidewalls, and not over the top surface, of the second copper-containing pillar. The first and the second protection layers include a compound of copper and a polymer, and are dielectric layers.

Abstract translation: 工件包括具有顶表面和侧壁的第一含铜柱，以及第一含铜柱的侧壁而不是顶表面上的第一保护层。 测试垫包括具有顶表面和侧壁的第二含铜柱。 测试垫电耦合到第一含铜柱。 第二保护层设置在第二含铜柱的侧壁上，而不是在顶表面上。 第一和第二保护层包括铜和聚合物的化合物，并且是电介质层。

公开(公告)号：US20130075892A1

公开(公告)日：2013-03-28

申请号：US13246553

申请日：2011-09-27

Applicant: Jing-Cheng Lin ,  Weng-Jin Wu ,  Ying-Ching Shih ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Weng-Jin Wu ,  Ying-Ching Shih ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/48 ,  H01L21/6835 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/83

Abstract: A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

Abstract translation: 一种用于制造三维集成电路的方法包括：提供其中多个半导体管芯安装在第一半导体管芯上的晶片堆叠，在第一半导体管芯的第一侧上形成模塑料层，其中多个半导体管芯被嵌入 在模塑料层中。 该方法还包括研磨第一半导体管芯的第二面直到多个通孔露出，将晶片堆叠附着到带框架上并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。

公开(公告)号：US08361895B2

公开(公告)日：2013-01-29

申请号：US12211464

申请日：2008-09-16

Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L21/22 ,  H01L21/38

CPC classification number: H01L29/66636 ,  H01L21/2254 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/49 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device and a method of manufacturing are provided. A substrate has a gate stack formed thereon. Ultra-shallow junctions are formed by depositing an atomic layer of a dopant and performing an anneal to diffuse the dopant into the substrate on opposing sides of the gate stack. The substrate may be recessed prior to forming the atomic layer and the recess may be filled by an epitaxial process. The depositing, annealing, and, if used, epitaxial growth may be repeated a plurality of times to achieve the desired junctions. Source/drain regions are also provided on opposing sides of the gate stack.

Abstract translation: 提供半导体器件和制造方法。 基板上形成有栅叠层。 通过沉积掺杂剂的原子层并执行退火来形成超浅结，以将掺杂剂扩散到栅叠层的相对侧上的衬底中。 衬底可以在形成原子层之前被凹入，并且凹槽可以通过外延工艺填充。 可以重复沉积，退火和（如果使用）外延生长以实现所需的结。 源极/漏极区域也设置在栅极堆叠的相对侧上。

公开(公告)号：US20130001776A1

公开(公告)日：2013-01-03

申请号：US13170973

申请日：2011-06-28

Applicant: Chen-Hua Yu ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Jui-Pin Hung ,  Shin-Puu Jeng

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Jui-Pin Hung ,  Shin-Puu Jeng

IPC: H01L23/485 ,  H01L21/28

CPC classification number: H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/214

Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.

Abstract translation: 封装包括具有基板的器件裸片。 模塑料与基材的侧壁接触。 金属焊盘在基板上。 钝化层具有覆盖金属焊盘的边缘部分的部分。 金属支柱已经过去并与金属垫接触。 介电层位于钝化层的上方。 由模塑料或聚合物形成的包装材料在电介质层的上面。 电介质层包括位于钝化层和封装材料之间的底部，以及在金属柱的侧壁和封装材料的侧壁之间的侧壁部分。 聚合物层在包装材料，模塑料和金属支柱之上。 后钝化互连（PPI）延伸到聚合物层中。 焊球在PPI上方，并通过PPI电耦合到金属焊盘。

公开(公告)号：US08199540B2

公开(公告)日：2012-06-12

申请号：US12683412

申请日：2010-01-06

Applicant: Ching-Shan Leu ,  Jing-Cheng Lin ,  Shun-Yuan Wu

Inventor： Ching-Shan Leu ,  Jing-Cheng Lin ,  Shun-Yuan Wu

IPC: H02J1/10 ,  H02J3/14 ,  H02M7/08 ,  H02M7/10

CPC classification number: H02M3/155 ,  H02M3/158 ,  H02M2001/009 ,  Y10T307/406

Abstract: A high voltage gain power converter includes: a main switch element; an assistant switch element; a first inductive element, a first switch element, and a first capacitive element; and a second inductive element, a second switch element, and a second capacitive element. The first inductive element is connected between an input node and first switch element. The first capacitive element, connected between the first switch element and ground, provides a first boost output voltage. The second inductive element is connected between the main switch element and first capacitive element. The second switch element is connected to a common node of the second inductive element and main switch element. The second capacitive element, connecting the second switch element to a first node, provides a second boost output voltage. The assistant switch element is connected between the first inductive element and common node of the second inductive element and main switch element.

Abstract translation: 高压增益功率转换器包括：主开关元件; 辅助开关元件; 第一电感元件，第一开关元件和第一电容元件; 以及第二感应元件，第二开关元件和第二电容元件。 第一电感元件连接在输入节点和第一开关元件之间。 连接在第一开关元件和地之间的第一电容元件提供第一升压输出电压。 第二电感元件连接在主开关元件和第一电容元件之间。 第二开关元件连接到第二电感元件和主开关元件的公共节点。 将第二开关元件连接到第一节点的第二电容元件提供第二升压输出电压。 辅助开关元件连接在第二电感元件和主开关元件的第一电感元件和公共节点之间。

公开(公告)号：US20120058628A1

公开(公告)日：2012-03-08

申请号：US13294526

申请日：2011-11-11

Applicant: Li-Shyue Lai ,  Jing-Cheng Lin

Inventor： Li-Shyue Lai ,  Jing-Cheng Lin

IPC: H01L21/20

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795

Abstract: A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric.

Abstract translation: 形成集成电路结构的方法包括：在半导体衬底中形成第一绝缘区域和第二绝缘区域并彼此面对; 以及形成具有反向T形的外延半导体区域。 外延半导体区域包括水平板，该水平板包括在第一绝缘区域和第二绝缘区域之间并邻接第一绝缘区域之间的底部，以及在水平板上并邻接的鳍状物。 水平板的底部接触半导体衬底。 该方法还包括在鳍的顶表面和至少顶部的顶部形成栅电介质; 以及在所述栅极电介质上形成栅电极。

公开(公告)号：US20120056315A1

公开(公告)日：2012-03-08

申请号：US12874952

申请日：2010-09-02

Applicant: Hsin Chang ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng

Inventor： Hsin Chang ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/03002 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00

Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.

Abstract translation: 一种器件包括衬底和包括穿透衬底的导电贯穿衬底通孔（TSV）的对准标记。

公开(公告)号：US08105875B1

公开(公告)日：2012-01-31

申请号：US12904835

申请日：2010-10-14

Applicant: Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

IPC: H01L21/50

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

Abstract translation: 一种方法包括提供包括衬底的中介层晶片，以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔（TSV）。 多个管芯结合到插入件晶片的前表面上。 在结合多个模具的步骤之后，在基板的背面进行研磨以暴露多个TSV。 多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。

公开(公告)号：US20120021604A1

公开(公告)日：2012-01-26

申请号：US12841874

申请日：2010-07-22

Applicant: Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin

Inventor： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin

IPC: H01L21/306 ,  H01L21/302 ,  H01L21/3065

CPC classification number: H01L21/6835 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: A method includes bonding a wafer on a carrier through an adhesive, and performing a thinning process on the wafer. After the step of performing the thinning process, a portion of the adhesive not covered by the wafer is removed, while the portion of the adhesive covered by the wafer is not removed.

Abstract translation: 一种方法包括通过粘合剂将晶片接合在载体上，并在晶片上进行稀化处理。 在进行稀化处理的步骤之后，去除未被晶片覆盖的粘合剂的一部分，同时由晶片覆盖的粘合剂部分未被除去。