公开(公告)号：US08350383B2

公开(公告)日：2013-01-08

申请号：US12503870

申请日：2009-07-16

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/04

CPC classification number: H01L23/49816 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01067 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An IC chip package, in one embodiment, may include an IC chip including an upper surface including an overhang extending beyond a sidewall of the IC chip, and underfill material about the sidewall and under the overhang. The overhang prevents underfill material from extending over an upper surface of the IC chip. In another embodiment, a ball grid array (BGA) is first mounted to landing pads on a lower of two joined IC chip packages. Since the BGA is formed on the lower IC chip package first, the BGA acts as a dam for the underfill material thereon. The underfill material extends about the respective IC chip and surrounds a bottom portion of a plurality of solder elements of the BGA and at least a portion of respective landing pads thereof.

Abstract translation: 在一个实施例中，IC芯片封装可以包括IC芯片，其包括包括延伸超过IC芯片的侧壁的突出部分的上表面，以及围绕侧壁和突出部分下方的底部填充材料。 悬垂防止底部填充材料在IC芯片的上表面上延伸。 在另一个实施例中，首先将球栅阵列（BGA）安装到两个连接的IC芯片封装的较低的焊盘上。 由于BGA首先形成在下部IC芯片封装上，所以BGA用作其上的底部填充材料的坝。 底部填充材料围绕相应的IC芯片延伸并围绕BGA的多个焊料元件的底部以及其各自的着陆焊盘的至少一部分。

公开(公告)号：US08338947B2

公开(公告)日：2012-12-25

申请号：US13361232

申请日：2012-01-30

Applicant: Timothy H. Daubenspeck ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Timothy D. Sullivan

IPC: H01L23/498

CPC classification number: H01L23/488 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45147 ,  H01L2224/48824 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of the solder bump pad, the current spreading pad comprising one or more layers, at least one of the one or more layers consisting of a material that will not form an intermetallic with tin or at least one of the one or more layers is a material that is a diffusion barrier to tin and adjacent to the solder bump pad.

公开(公告)号：US08298904B2

公开(公告)日：2012-10-30

申请号：US13008465

申请日：2011-01-18

Applicant: Joseph M. Lukaitis ,  Jed H. Rankin ,  Robert R. Robison ,  Dustin K. Slisher ,  Timothy D. Sullivan

Inventor： Joseph M. Lukaitis ,  Jed H. Rankin ,  Robert R. Robison ,  Dustin K. Slisher ,  Timothy D. Sullivan

IPC: H01L21/20

CPC classification number: H01L27/1203 ,  H01L28/20

Abstract: A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate, and forming at least one dielectric layer over the resistor. The method also includes forming a substrate contact through the at least one dielectric layer, through the resistor, through the insulator layer, and into the substrate. The substrate contact comprises a high thermal conductivity material.

Abstract translation: 形成半导体结构的方法包括在衬底上的绝缘体层上形成电阻器，并且在电阻器上方形成至少一个电介质层。 所述方法还包括通过所述至少一个电介质层，通过所述电阻器，穿过所述绝缘体层，并进入所述衬底形成衬底接触。 衬底接触包括高导热性材料。

公开(公告)号：US20120139123A1

公开(公告)日：2012-06-07

申请号：US12960110

申请日：2010-12-03

Applicant: Timothy H. Daubenspeck ,  Gary Lafontant ,  Ekta Misra ,  David L. Questad ,  George J. Scott ,  Krystyna W. Semkow ,  Timothy D. Sullivan ,  Thomas A. Wassick ,  Steven L. Wright

Inventor： Timothy H. Daubenspeck ,  Gary Lafontant ,  Ekta Misra ,  David L. Questad ,  George J. Scott ,  Krystyna W. Semkow ,  Timothy D. Sullivan ,  Thomas A. Wassick ,  Steven L. Wright

IPC: H01L23/52 ,  G06F17/50 ,  H01L21/44

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13006 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/3511 ,  Y02P90/265 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Semiconductor structures, methods of manufacture and design structures are provided. The structure includes at least one offset crescent shaped solder via formed in contact with an underlying metal pad of a chip. The at least one offset crescent shaped via is offset with respect to at least one of the underlying metal pad and an underlying metal layer in direct electrical contact with an interconnect of the chip which is in electrical contact with the underlying metal layer.

Abstract translation: 提供半导体结构，制造方法和设计结构。 该结构包括与芯片的下面的金属焊盘接触形成的至少一个偏移月牙形焊料通孔。 至少一个偏移月牙形通孔相对于下面的金属焊盘和下面的金属层中的至少一个与芯片的与下面的金属层电接触的互连直接电接触而偏移。

公开(公告)号：US20120122260A1

公开(公告)日：2012-05-17

申请号：US13357728

申请日：2012-01-25

Applicant: Ethan H. Cannon ,  Michael J. Hauser ,  Timothy D. Sullivan

Inventor： Ethan H. Cannon ,  Michael J. Hauser ,  Timothy D. Sullivan

IPC: H01L31/18

CPC classification number: H01L31/115 ,  H01L23/552 ,  H01L23/556 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An array of radiation sensors or detectors is integrated within a three-dimensional semiconductor IC. The sensor array is located relatively close to the device layer of a circuit (e.g., a microprocessor) to be protected from the adverse effects of the ionizing radiation particles. As such, the location where the radiation particles intersect the device layer can be calculated with coarse precision (e.g., to within 10 s of microns).

Abstract translation: 辐射传感器或检测器阵列集成在三维半导体IC内。 传感器阵列相对靠近电路（例如，微处理器）的器件层定位，以防止电离辐射粒子的不利影响。 因此，辐射粒子与器件层相交的位置可以用粗精度（例如，在10微米以内）来计算。

公开(公告)号：US08159067B2

公开(公告)日：2012-04-17

申请号：US12190612

申请日：2008-08-13

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Marie-Claude Paquet ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Marie-Claude Paquet ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/48

CPC classification number: H01L21/56 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/743 ,  H01L24/97 ,  H01L29/0657 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes.

Abstract translation: 底部填充流动引导结构及其使用方法具有模块。 特别地，底部填充流动引导结构与基底一体化并且被构造成防止在毛细管底部填充过程期间发生空气滞留。

公开(公告)号：US20120061832A1

公开(公告)日：2012-03-15

申请号：US12879602

申请日：2010-09-10

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/485

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/034 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: In one embodiment, a collar structure includes a non-conductive layer that relieves stress around the perimeter of each of the solder balls that connect the semiconductor die to the semiconductor chip package substrate, and another non-conductive layer placed underneath to passivate the entire surface of the die.

Abstract translation: 在一个实施例中，套环结构包括非导电层，其将围绕将半导体管芯连接到半导体芯片封装衬底的每个焊球的周边释放应力，以及放置在其下方以钝化整个表面的另一非导电层 的死亡。

公开(公告)号：US08120131B2

公开(公告)日：2012-02-21

申请号：US12547519

申请日：2009-08-26

Applicant: Ethan H. Cannon ,  Michael J. Hauser ,  Timothy D. Sullivan

Inventor： Ethan H. Cannon ,  Michael J. Hauser ,  Timothy D. Sullivan

IPC: H01L31/02

CPC classification number: H01L31/115 ,  H01L23/552 ,  H01L23/556 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An array of radiation sensors or detectors is integrated within a three-dimensional semiconductor IC. The sensor array is located relatively close to the device layer of a circuit (e.g., a microprocessor) to be protected from the adverse effects of the ionizing radiation particles. As such, the location where the radiation particles intersect the device layer can be calculated with coarse precision (e.g., to within 10 s of microns).

Abstract translation: 辐射传感器或检测器阵列集成在三维半导体IC内。 传感器阵列相对靠近电路（例如，微处理器）的器件层定位，以防止电离辐射粒子的不利影响。 因此，辐射粒子与器件层相交的位置可以用粗精度（例如，在10微米以内）来计算。

公开(公告)号：US08084864B2

公开(公告)日：2011-12-27

申请号：US13114342

申请日：2011-05-24

Applicant: Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

Inventor： Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76834 ,  H01L21/32051 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76858 ,  H01L2221/1078

Abstract: A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl3 liner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAl3 liner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAl3 liner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.

Abstract translation: 在下面的金属互连结构上形成由元素金属衬垫，金属氮化物衬垫，Ti衬垫，铝部分和金属氮化物盖的从底部到顶部的垂直金属堆叠。 垂直金属叠层在升高的温度下退火，以通过Ti衬垫与铝部分的材料反应而引起TiAl 3衬层的形成。 TiAl 3衬垫的材料对电迁移是耐受的，从而对包括元素金属衬垫，金属氮化物衬垫，TiAl 3衬里，铝部分和金属氮化物盖的垂直金属堆叠提供增强的电迁移阻力。 在金属氮化物盖在加工过程中遭受侵蚀的区域中，增强的耐电迁移性的作用可能更为突出。

公开(公告)号：US20110221064A1

公开(公告)日：2011-09-15

申请号：US13114342

申请日：2011-05-24

Applicant: Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

Inventor： Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

IPC: H01L23/522

CPC classification number: H01L21/76834 ,  H01L21/32051 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76858 ,  H01L2221/1078

Abstract: A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl3 liner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAl3 liner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAl3 liner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.

Abstract translation: 在下面的金属互连结构上形成由元素金属衬垫，金属氮化物衬垫，Ti衬垫，铝部分和金属氮化物盖的从底部到顶部的垂直金属堆叠。 垂直金属叠层在升高的温度下退火，以通过Ti衬垫与铝部分的材料反应而引起TiAl 3衬层的形成。 TiAl 3衬垫的材料对电迁移是耐受的，从而对包括元素金属衬垫，金属氮化物衬垫，TiAl 3衬里，铝部分和金属氮化物盖的垂直金属堆叠提供增强的电迁移阻力。 在金属氮化物盖在加工过程中遭受侵蚀的区域中，增强的耐电迁移性的作用可能更为突出。