公开(公告)号：US20050125751A1

公开(公告)日：2005-06-09

申请号：US11038744

申请日：2005-01-18

Applicant: Charles Miller ,  John Long

Inventor： Charles Miller ,  John Long

IPC: H01L23/522 ,  H01L23/60 ,  G06F17/50

CPC classification number: H01L24/49 ,  H01L23/5227 ,  H01L23/60 ,  H01L24/45 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/49113 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A method for designing integrated circuits (ICs) and their interconnect systems includes IC component cells and interconnect component cells in a cell library. Each IC component cell provides both a physical and behavioral model of a component that may be incorporated into the IC while each interconnect component cell includes both a physical and behavioral model of a separate internal or external component of an interconnect system that may link the IC to external nodes. Both the IC and its interconnect systems are designed by selecting and specifying interconnections between component cells included in the cell library. Interconnect systems are flexibily designed to act like filters tuned to optimize desired frequency response characteristics. Behavior models of the IC and its interconnect systems, based on the behavior models of their selected component, are subjected to simulation and verification tools to determine whether the IC and its interconnect systems meet various performance criteria and constraints. The structural models of the interconnect systems developed during the design process guide subsequent fabrication of interconnect systems for both the IC's intended testing and operating environments.

Abstract translation: 集成电路（IC）及其互连系统的设计方法包括IC元件单元和单元库中的互连元件单元。 每个IC组件单元提供可以并入到IC中的组件的物理和行为模型，而每个互连组件单元包括互连系统的单独的内部或外部组件的物理和行为模型，其可将IC连接到 外部节点。 通过选择和指定包含在单元库中的组件单元之间的互连来设计IC及其互连系统。 互连系统灵活设计为像调谐滤波器一样起作用，以优化所需的频率响应特性。 基于其所选组件的行为模型，IC及其互连系统的行为模型受到仿真和验证工具的影响，以确定IC及其互连系统是否符合各种性能标准和约束。 在设计过程中开发的互连系统的结构模型指导随后为IC的预期测试和操作环境制造互连系统。

公开(公告)号：US20050001638A1

公开(公告)日：2005-01-06

申请号：US10832700

申请日：2004-04-27

Applicant: Charles Miller ,  John Long

Inventor： Charles Miller ,  John Long

IPC: G01R1/073 ,  H05K1/00 ,  H05K1/02 ,  G01R31/02

CPC classification number: G01R31/31926 ,  G01R1/07378 ,  G01R31/318511 ,  G11C29/56 ,  G11C2029/2602 ,  H05K1/0216 ,  H05K1/023 ,  H05K1/0289 ,  H05K2201/09254 ,  Y10T29/49117

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.

Abstract translation: 互连结构采用闭合栅格总线将集成电路测试器通道连接到半导体晶片上的输入/输出（I / O）焊盘阵列，使得测试仪通道可以同时与所有I / O焊盘通信。 互连结构包括实现总线节点阵列的电路板，每个总线节点对应于单独的一个I / O焊盘。 电路板包括至少两层。 安装在第一层上的轨迹形成一组第一个菊花链总线，每个链路总线连接总线节点阵列的单独行的所有总线节点。 安装在第二电路板层上的迹线形成一组第二菊花链总线，每条链路总线连接总线节点阵列的单独列的所有总线节点。 第一和第二菊花链总线的通路和其他电路板互连端，使得它们形成闭合栅格总线。 每个总线节点通过单独的隔离电阻器连接到安装在电路板表面上的单独的接触焊盘。 一组弹簧触点或探针将每个接触垫连接到晶片上的单独的I / O焊盘之间。

公开(公告)号：US20040266089A1

公开(公告)日：2004-12-30

申请号：US10852370

申请日：2004-05-24

Applicant: FormFactor, Inc.

Inventor： Gaetan L. Mathieu ,  Benjamin N. Eldridge ,  Gary W. Grube

IPC: H01L021/8238

CPC classification number: G01R1/07307 ,  G01R3/00

Abstract: A planarizer for a probe card assembly. A planarizer includes a first control member extending from a substrate in a probe card assembly. The first control member extends through at least one substrate in the probe card assembly and is accessible from an exposed side of an exterior substrate in the probe card assembly. Actuating the first control member causes a deflection of the substrate connected to the first control member.

Abstract translation: 用于探针卡组件的平面化器。 平面化器包括从探针卡组件中的衬底延伸的第一控制构件。 第一控制构件延伸穿过探针卡组件中的至少一个衬底，并且可从探针卡组件中的外部衬底的暴露侧进入。 驱动第一控制构件导致连接到第一控制构件的衬底的偏转。

公开(公告)号：US20040203262A1

公开(公告)日：2004-10-14

申请号：US10411175

申请日：2003-04-10

Applicant: FormFactor, Inc.

Inventor： Scott E. Lindsey ,  Charles A. Miller ,  David M. Royster ,  Stuart W. Wenzel

IPC: H01R012/00

CPC classification number: G01R1/06733 ,  G01R1/06711 ,  G01R1/06744 ,  G01R31/2884 ,  H01L21/4853 ,  H01L23/49811 ,  H01L2224/16 ,  H01L2924/00014 ,  H01R4/4863 ,  H01R12/57 ,  H01R13/035 ,  H01R13/2421 ,  H01R13/33 ,  H01R43/16 ,  H05K3/326 ,  H05K3/4007 ,  H05K3/4092 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/10265 ,  H05K2203/308 ,  H01L2224/0401

Abstract: A microelectronic spring contact for making electrical contact between a device and a mating substrate and method of making the same are disclosed. The spring contact has a compliant pad adhered to a substrate of the device and spaced apart from a terminal of the device. The compliant pad has a base adhered to the substrate, and side surfaces extending away from the substrate and tapering to a smaller end area distal from the substrate. A trace extends from the terminal of the device in a coil pattern over the compliant pad to its end area, forming a helix. At least a portion of the compliant pad end area is covered by the trace, and a portion of the trace that is over the compliant pad is supported by the compliant pad. In an alternative embodiment, the pad is removed to leave a freestanding helical contact.

Abstract translation: 公开了一种用于在器件和匹配衬底之间进行电接触的微电子弹簧触点及其制造方法。 弹簧触点具有粘附到装置的基板并与装置的端子间隔开的柔性衬垫。 柔性衬垫具有粘附到衬底的基底，以及远离衬底延伸的侧表面，并且逐渐变细到远离衬底的较小端部区域。 迹线从器件的端子以柔性衬垫的线圈图案延伸到其端部区域，形成螺旋线。 柔性焊盘端部区域的至少一部分被迹线覆盖，并且位于柔性焊盘上方的迹线的一部分由柔性焊盘支撑。 在替代实施例中，去除垫以留下独立的螺旋接触。

公开(公告)号：US20040201392A1

公开(公告)日：2004-10-14

申请号：US10411179

申请日：2003-04-10

Applicant: FormFactor, Inc.

Inventor： Tae Ma Kim ,  Bunsaku Nagai

IPC: G01R031/02

CPC classification number: G01R1/06744 ,  G01R1/06794 ,  G01R3/00 ,  G01R31/2891

Abstract: An image of an array of probes is searched for alignment features. The alignment features are then used to bring contact targets and the probes into contact with one another. The alignment features may be a feature of one or more of the tips of the probes. For example, such a feature may be a corner of one of the tips. An array of probes may be formed to have such alignment features.

Abstract translation: 搜索探针阵列的图像以获得对准特征。 然后将对准特征用于使接触目标和探针彼此接触。 对准特征可以是探针的一个或多个尖端的特征。 例如，这样的特征可以是其中一个提示的一角。 可以形成探针阵列以具有这样的对准特征。

公开(公告)号：US20040107568A1

公开(公告)日：2004-06-10

申请号：US10310791

申请日：2002-12-06

Applicant: FormFactor, Inc.

Inventor： Igor Y. Khandros ,  Gaetan L. Mathieu ,  Carl V. Reynolds

IPC: H05K001/00 ,  B23P019/00 ,  H05K003/30

CPC classification number: G01R3/00 ,  G01R1/0433 ,  G01R1/0483 ,  G01R1/07378 ,  G01R31/2863 ,  H01L24/13 ,  H01L2224/131 ,  H01L2924/01046 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49169 ,  Y10T29/49179 ,  Y10T29/49197 ,  Y10T29/49204 ,  Y10T29/4921 ,  Y10T29/49211 ,  Y10T29/49224 ,  Y10T29/53217 ,  Y10T29/53265 ,  H01L2924/014

Abstract: A interconnect structure is inexpensively manufactured and easily insertable into a socket. The interconnect structure is manufactured by forming a sacrificial substrate with cavities that is covered by a masking material having openings corresponding to the cavities. A first plating process is performed by depositing conductive material, followed by coupling wires within the openings and performing another plating process by depositing more conductive material. The interconnect structure is completed by first removing the masking material and sacrificial substrate. Ends of the wires are coupled opposite now-formed contact structures to a board. To complete the socket, a support device is coupled to the board to hold a tested integrated circuit.

Abstract translation: 互连结构廉价地制造并且容易地插入到插座中。 通过形成具有由具有与空腔对应的开口的掩模材料覆盖的空腔的牺牲基板来制造互连结构。 通过沉积导电材料，然后在开口内连接线并通过沉积更多导电材料进行另一电镀工艺来执行第一电镀工艺。 通过首先去除掩模材料和牺牲衬底来完成互连结构。 电线的端部与现在形成的接触结构相对联接到电路板。 要完成插座，支持设备耦合到电路板以保持测试的集成电路。

公开(公告)号：US20040058487A1

公开(公告)日：2004-03-25

申请号：US10667689

申请日：2003-09-22

Applicant: FormFactor, Inc.

Inventor： Mohammad Eslamy ,  David V. Pedersen ,  Harry D. Cobb

IPC: H01L021/8238

CPC classification number: G01R31/2886 ,  G01R3/00 ,  Y10T29/49004 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49171 ,  Y10T29/49178 ,  Y10T29/49204 ,  Y10T29/4921 ,  Y10T29/49211

Abstract: A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.

Abstract translation: 一种制造大面积多元件接触器的方法。 提供分段接触器用于测试晶片上的半导体器件，其包括安装到衬底的多个接触器单元。 接触器单元被形成，测试和组装到背衬基板上。 接触器单元可以包括横向延伸的引线以连接到诸如老化板的外部仪器。 接触器单元包括诸如焊盘的导电区域，其被放置成与被测器件上的导电端子接触。

公开(公告)号：US20040016119A1

公开(公告)日：2004-01-29

申请号：US10202712

申请日：2002-07-24

Applicant: FormFactor, Inc.

Inventor： Benjamin N. Eldridge ,  Gaetan L. Mathieu ,  Carl V. Reynolds

IPC: H01R043/20 ,  H05K003/30

CPC classification number: G01R1/06744 ,  G01R1/06733 ,  G01R3/00 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49222 ,  Y10T29/49224

Abstract: A method of making a microelectronic spring contact array comprises forming a plurality of spring contacts on a sacrificial substrate and then releasing the spring contacts from the sacrificial substrate. Each of the spring contacts has an elongated beam having a base end. The method of making the array includes attaching the spring contacts at their base ends to a base substrate after they have been released entirely from the sacrificial substrate, so that each contact extends from the base substrate to a distal end of its beams. The distal ends are aligned with a predetermined array of tip positions. In an embodiment of the invention, the spring contacts are formed by patterning contours of the spring contacts in a sacrificial layer on the sacrificial substrate. The walls of patterned recesses in the sacrificial layer define side profiles of the spring contacts, and a conductive material is deposited in the recesses to form the elongated beams of the spring contacts.

Abstract translation: 制造微电子弹簧接触阵列的方法包括在牺牲衬底上形成多个弹簧触点，然后从牺牲衬底释放弹簧触头。 每个弹簧触点具有带有基端的细长梁。 制造阵列的方法包括在它们已经从牺牲基板完全释放之后将其基端处的弹簧触点附接到基底基板，使得每个触点从基底延伸到其波束的远端。 远端与预定阵列的尖端位置对准。 在本发明的一个实施例中，通过在牺牲衬底上的牺牲层中图形地形成弹簧触点的轮廓来形成弹簧触点。 牺牲层中的图案化凹槽的壁限定弹簧触点的侧面轮廓，并且导电材料沉积在凹部中以形成弹簧触点的细长梁。

公开(公告)号：US20030237061A1

公开(公告)日：2003-12-25

申请号：US10177367

申请日：2002-06-19

Applicant: FormFactor, Inc.

Inventor： Charles A. Miller ,  Timothy Cooper ,  Yoshikazu Hatsukano

IPC: G06F017/50 ,  H01L029/40

CPC classification number: G11C29/56 ,  G01R31/2831 ,  G01R31/2886 ,  G01R31/31718 ,  G11C29/006 ,  G11C29/56016

Abstract: A semiconductor wafer is cut to singulate integrated circuit dice formed on the wafer. A die pick machine then positions and orients the singulated dice on a carrier base such that signal, power and ground pads formed on the surface of each die reside at predetermined positions relative to landmarks on the carrier base the die pick machine optically identifies. With the dice temporarily held in place on the carrier base, they are subjected to a series of testing and other processing steps. Since each die's signal pads reside in predetermined locations, they can be accessed by appropriately arranged probes providing test equipment with signal access to the pads during tests. After each test, a die pick machine may replace any die that fails the test with another die, thereby improving efficiency of subsequent testing and other processing resources.

Abstract translation: 切割半导体晶片以对形成在晶片上的集成电路芯片进行分割。 然后，骰子拾取机器将分离的骰子定位和定位在载体基座上，使得形成在每个模具表面上的信号，功率和接地垫相对于骰子拾取机器光学识别的载体基座上的标志位于预定位置。 将骰子临时固定在承运人基地上，对其进行一系列测试和其他处理步骤。 由于每个管芯的信号焊盘都位于预定位置，所以它们可以通过适当布置的探头进行访问，从而在测试期间为测试设备提供对焊盘的信号访问。 在每次测试之后，模具拾取机器可以用另一个模具代替未测试的任何模具，从而提高后续测试和其他处理资源的效率。

公开(公告)号：US20030222667A1

公开(公告)日：2003-12-04

申请号：US10458875

申请日：2003-06-10

Applicant: FormFactor, Inc.

Inventor： Igor Y. Khandros JR. ,  A. Nicholas Sporck ,  Benjamin N. Eldridge JR.

IPC: G01R031/02

CPC classification number: H05K3/4015 ,  B23K1/0016 ,  B23K20/004 ,  B23K2101/40 ,  C25D5/08 ,  C25D5/22 ,  C25D21/02 ,  G01R1/06711 ,  G01R1/07342 ,  G01R1/07364 ,  G01R1/07378 ,  G01R31/2886 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L21/76897 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01R12/52 ,  H05K1/141 ,  H05K3/20 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K3/4092 ,  H05K7/1069 ,  H05K2201/0397 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05599

Abstract: In a probe card assembly, a series of probe elements can be arrayed on a silicon space transformer. The silicon space transformer can be fabricated with an array of primary contacts in a very tight pitch, comparable to the pitch of a semiconductor device. One preferred primary contact is a resilient spring contact. Conductive elements in the space transformer are routed to second contacts at a more relaxed pitch. In one preferred embodiment, the second contacts are suitable for directly attaching a ribbon cable, which in turn can be connected to provide selective connection to each primary contact. The silicon space transformer is mounted in a fixture that provides for resilient connection to a wafer or device to be tested. This fixture can be adjusted to planarize the primary contacts with the plane of a support probe card board.

Abstract translation: 在探针卡组件中，可以将一系列探针元件排列在硅空间变压器上。 硅空间变压器可以以与半导体器件的间距相当的非常紧密的间距的主要触点阵列制造。 一个优选的主要接触是弹性弹簧接触。 空间变压器中的导电元件以更放松的间距被路由到第二触点。 在一个优选实施例中，第二触点适于直接连接带状电缆，带状电缆又可连接以提供对每个主触点的选择性连接。 硅空间变压器安装在固定装置中，其提供与待测试的晶片或装置的弹性连接。 可以调整该夹具以使主触头与支撑探针卡板的平面平坦化。