公开(公告)号：US20170012013A1

公开(公告)日：2017-01-12

申请号：US15271744

申请日：2016-09-21

Applicant: FUJITSU LIMITED

Inventor： KOZO SHIMIZU ,  Seiki Sakuyama

IPC: H01L23/00 ,  H01L23/498 ,  B23K35/26 ,  H01L23/31 ,  B23K1/00 ,  B23K35/02

CPC classification number: H01L24/17 ,  B23K1/0008 ,  B23K1/0016 ,  B23K3/085 ,  B23K35/0244 ,  B23K35/262 ,  B23K35/264 ,  B23K2101/40 ,  B23K2101/42 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05082 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/13016 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16145 ,  H01L2224/16157 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/16505 ,  H01L2224/16507 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/75253 ,  H01L2224/75501 ,  H01L2224/75502 ,  H01L2224/759 ,  H01L2224/81005 ,  H01L2224/81075 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2224/81948 ,  H01L2224/81986 ,  H01L2225/06513 ,  H01L2924/014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/1579 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/16747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3512 ,  H01L2924/35121 ,  H05K1/0203 ,  H05K1/09 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0248 ,  H05K2201/09972 ,  H05K2201/1056 ,  H05K2203/1121 ,  H05K2203/304 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/00

Abstract: An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

Abstract translation: 电子设备包括具有第一端子的第一电子部件，与第一端子相对的第二端子的第二电子部件和与第一端子和第二端子连接的接合部。 接合部分包含在第一端子和第二端子彼此相对的方向上延伸的极性化合物。 接合部分包含杆状化合物，从而提高接合部分的强度。 当第一端子和第二端子接合时，第一电子部件和第二电子部件之一的温度被制成高于另一端子的温度。 在该状态下将接合材料冷却并固化。 通过这样做，形成极点状化合物。

公开(公告)号：US20160344102A1

公开(公告)日：2016-11-24

申请号：US14717172

申请日：2015-05-20

Applicant: Google Inc.

Inventor： Peter Bevelacqua ,  Jason Chamberlain

IPC: H01Q7/00 ,  H05K3/32 ,  H01Q1/38

CPC classification number: H01Q7/00 ,  H01Q1/38 ,  H04B5/0056 ,  H04B5/0081 ,  H05K1/0296 ,  H05K3/32 ,  H05K2201/09063 ,  H05K2201/09972 ,  H05K2201/10098

Abstract: Systems and techniques are provided for a co-located NFC reader. A top conductive layer may include an inner PCB section, including a circuit for an electronic device, and an outer PCB section, including a near-field communications (NFC) chipset, separated by a gap in which an NFC antenna connected to the NFC chipset may be located. A substrate layer may include an inner PCB section and an outer PCB section separated by the gap. A bridge including a trace may cross the gap. A lower conductive layer may include an inner PCB section, including a circuit for the electronic device electrically connected to the circuit for the electronic device located on the inner PCB section of the top conductive layer, and an outer PCB section, including a circuit for the electronic device, separated by the gap.

Abstract translation: 为同位置的NFC读取器提供了系统和技术。 顶部导电层可以包括内部PCB部分，其包括用于电子设备的电路，以及外部PCB部分，其包括近场通信（NFC）芯片组，所述近场通信（NFC）芯片组由连接到NFC芯片组的NFC天线间隔开 可能位于。 衬底层可以包括由间隙分开的内部PCB部分和外部PCB部分。 包括痕迹的桥梁可能会跨越这个空白。 下部导电层可以包括内部PCB部分，其包括用于电连接到位于顶部导电层的内部PCB部分上的电子设备的电路的电子设备的电路，以及外部PCB部分，其包括用于 电子设备，隔开间隔。

公开(公告)号：US20150373847A1

公开(公告)日：2015-12-24

申请号：US14496876

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Kevin E. Wells ,  Richard C. Stamey

IPC: H05K1/11 ,  H05K3/42 ,  G06F1/16 ,  H05K3/36 ,  H05K1/02 ,  H05K7/02

CPC classification number: G06F1/16 ,  H01L2924/0002 ,  H05K1/115 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/421 ,  H05K3/4694 ,  H05K2201/041 ,  H05K2201/09972 ,  H05K2201/10159 ,  H05K2201/10719 ,  Y02P70/613 ,  Y10T29/49128 ,  H01L2924/00

Abstract: Described are apparatuses for modular printed circuit boards (PCB) and methods for producing modular PCBs. An apparatus may include a first PCB module with a first pattern of routing structures on one or more layers of the first PCB module. The apparatus may further include a second PCB module with a second pattern of routing structures on one or more layers of the second PCB module. The second pattern of routing structures may be aligned with and electrically coupled to the first pattern of routing structures without connectors. Other embodiments may be described and/or claimed.

Abstract translation: 描述了用于模块化印刷电路板（PCB）的装置和用于制造模块化PCB的方法。 装置可以包括具有在第一PCB模块的一个或多个层上的路由结构的第一图案的第一PCB模块。 该装置还可以包括具有在第二PCB模块的一个或多个层上的路由结构的第二图案的第二PCB模块。 路由结构的第二模式可以与没有连接器的路由结构的第一模式对准并电耦合。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20150271959A1

公开(公告)日：2015-09-24

申请号：US14308386

申请日：2014-06-18

Applicant: Apple Inc.

Inventor： Yanfeng Chen ,  Shankar S. Pennathur

IPC: H05K9/00

CPC classification number: H05K9/0024 ,  H01L2924/1815 ,  H01L2924/3025 ,  H05K1/0215 ,  H05K1/0218 ,  H05K3/284 ,  H05K9/0039 ,  H05K2201/0715 ,  H05K2201/0723 ,  H05K2201/09972 ,  H05K2201/1056

Abstract: A portable electronic device packaged into a System-in-Package assembly is disclosed. The portable electronic device can include a substrate and a plurality of components mounted on the substrate and included in one or more subsystems. Interference between subsystems or from external sources can be reduced or eliminated by disposing an insulating layer over the components, forming narrow trenches between subsystems, and conformally coating the insulating layer and trenches with a metal shielding layer. In some examples, trenches between subsystems can be formed using a laser source. In some examples, trenches between subsystems can have angled walls. In some examples, the metal shielding layer can be formed using at least one of electroplating, electroless plating, chemical vapor deposition, and physical vapor deposition.

Abstract translation: 公开了一种封装在系统级封装中的便携式电子设备。 便携式电子设备可以包括基板和安装在基板上并包括在一个或多个子系统中的多个部件。 通过在部件之间设置绝缘层，在子系统之间形成窄沟槽，并用金属屏蔽层保形地涂覆绝缘层和沟槽，可以减少或消除子系统之间或外部源之间的干扰。 在一些示例中，子系统之间的沟槽可以使用激光源形成。 在一些示例中，子系统之间的沟槽可以具有成角度的壁。 在一些示例中，可以使用电镀，化学镀，化学气相沉积和物理气相沉积中的至少一种来形成金属屏蔽层。

公开(公告)号：US20150257275A1

公开(公告)日：2015-09-10

申请号：US14634972

申请日：2015-03-02

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Yasuhiko KUSAMA ,  Hideyuki TAKO ,  Kenji KAWAI ,  Fumihisa MIYASAKA

IPC: H05K1/18

CPC classification number: H05K1/185 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15313 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/09972

Abstract: A wiring substrate includes a core layer having a hole penetrating therethrough in a thickness direction thereof, and having a projecting part projecting from an inner wall of the hole toward an inner space of the hole, the projecting part being situated at a border that divides a plurality of areas in the hole, a plurality of electronic components disposed in the areas, respectively, the electronic components being arranged at a spaced interval with the projecting part therebetween, and a resin layer filling the hole and supporting the electronic components, wherein a thickness of the projecting part in the thickness direction of the core layer decreases toward a tip of the projecting part.

Abstract translation: 布线基板包括芯层，该芯层在其厚度方向上具有贯穿其中的孔，并且具有从孔的内壁朝向孔的内部空间突出的突出部分，突出部分位于边界处， 所述孔中的多个区域，分别设置在所述区域中的多个电子部件，所述电子部件以与所述突出部分间隔开的间隔布置，以及填充所述孔并支撑所述电子部件的树脂层，其中， 在芯层的厚度方向上的突出部分朝向突出部分的尖端减小。

公开(公告)号：US20150245485A1

公开(公告)日：2015-08-27

申请号：US14628477

申请日：2015-02-23

Applicant: IBIDEN CO., LTD.

Inventor： Nobuya TAKAHASHI ,  Shigeru YAMADA ,  Takashi KARIYA

IPC: H05K1/11 ,  H05K3/18 ,  H05K3/30

CPC classification number: H05K1/113 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/4694 ,  H05K2201/094 ,  H05K2201/09972 ,  H05K2201/10522 ,  H05K2201/10674 ,  Y10T29/49144

Abstract: A printed wiring board includes a first insulating layer, a first conductor layer formed on a surface of the first insulating layer and including first pads, and a wiring structure including a second conductor layer formed on the first insulating layer, a second insulating layer laminated on the second conductor layer, a third conductor layer formed on the second insulating layer, and formed through the second insulating layer. The second conductor layer includes second pads formed on the first insulating layer, the third conductor layer includes third pads formed on the second insulating layer, the via conductors are positioned such that the via conductors are connecting the second pads and the third conductor layer, and the wiring structure is formed such that the second conductor layer and third conductor layer are not electrically connected to the first conductor layer.

Abstract translation: 印刷布线板包括第一绝缘层，形成在第一绝缘层的表面上并包括第一焊盘的第一导体层，以及包括形成在第一绝缘层上的第二导体层的布线结构，层叠在第一绝缘层上的第二绝缘层 第二导体层，形成在第二绝缘层上的第三导体层，并通过第二绝缘层形成。 所述第二导体层包括形成在所述第一绝缘层上的第二焊盘，所述第三导体层包括形成在所述第二绝缘层上的第三焊盘，所述通孔导体定位成使得所述通孔导体连接所述第二焊盘和所述第三导体层，以及 布线结构形成为使得第二导体层和第三导体层不与第一导体层电连接。

公开(公告)号：US20150245471A1

公开(公告)日：2015-08-27

申请号：US14615772

申请日：2015-02-06

Applicant: DENSO CORPORATION

Inventor： Hirotsugu KATOU ,  Junji SUGIURA ,  Akito ITOU

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K1/0286 ,  H05K2201/09781 ,  H05K2201/09972

Abstract: An electronic device includes a multilayer substrate including a plurality of layers of conductors. The multilayer substrate has a first region and a second region divided in a planar direction of the multilayer substrate. The first region is provided with a main circuit that realizes a predetermined function. The second region is provided to have an additional circuit for adding a function to the predetermined function therein. The first region includes a first wiring for electrically connecting the main circuit to the additional circuit and a connecting portion disposed at an end of the first region adjacent to the second region and extending in the multilayer substrate to correspond to all of the conductors layered to electrically connect the first wiring to any of the conductors. The main circuit is connectable with the additional circuit through the first wiring and the connecting portion.

Abstract translation: 电子设备包括包括多层导体的多层衬底。 多层基板具有在多层基板的平面方向上划分的第一区域和第二区域。 第一区域设置有实现预定功能的主电路。 第二区域设置成具有用于向其中的预定功能添加功能的附加电路。 第一区域包括用于将主电路电连接到附加电路的第一布线和设置在与第二区域相邻的第一区域的端部处并在多层基板中延伸的连接部分，以对应于分层到电的所有导体 将第一个接线连接到任何导体。 主电路可通过第一布线和连接部分与附加电路连接。

公开(公告)号：US20150239407A1

公开(公告)日：2015-08-27

申请号：US14609742

申请日：2015-01-30

Applicant: DENSO CORPORATION

Inventor： Akito ITOU ,  Junji SUGIURA ,  Hirotsugu KATO

IPC: B60R16/023 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K1/181 ,  H05K1/0231 ,  H05K1/0262 ,  H05K2201/0746 ,  H05K2201/09972

Abstract: An electronic control device for executing fundamental and additional functions includes: a fundamental circuit element that executes the fundamental function; an additional circuit element that executes the additional function; and a printed wiring board having a rectangular shape divided into first and second regions. The fundamental circuit element is mounted in the first region, and the additional circuit element is mounted in the second region. The fundamental circuit element includes an operation voltage generating circuit for supplying an operation voltage to at least a part of the fundamental and additional circuit elements and a bypass capacitor for functioning for the additional circuit element. The bypass capacitor is connected to a power source wiring pattern for supplying the operation voltage to the additional circuit element. The bypass capacitor is arranged in the first region at a position nearer the second region than the operation voltage generating circuit.

Abstract translation: 用于执行基本和附加功能的电子控制装置包括：执行基本功能的基本电路元件; 执行附加功能的附加电路元件; 以及划分为第一和第二区域的具有矩形形状的印刷线路板。 基本电路元件安装在第一区域中，并且附加电路元件安装在第二区域中。 基本电路元件包括用于向至少一部分基波和附加电路元件提供操作电压的操作电压产生电路和用于附加电路元件的旁路电容器。 旁路电容器连接到用于向附加电路元件提供工作电压的电源布线图案。 旁路电容器布置在比操作电压产生电路更靠近第二区域的位置处的第一区域中。

公开(公告)号：US20150189794A1

公开(公告)日：2015-07-02

申请号：US14582877

申请日：2014-12-24

Applicant: DENSO CORPORATION

Inventor： Tsuyoshi TASHIMA ,  Jyunichi OOGOSHI ,  Takayuki UCHIDA ,  Katsuhiko HAYASHI ,  Shinsuke OOTA

IPC: H05K7/20 ,  B62D5/04

CPC classification number: B62D5/0406 ,  H05K1/0203 ,  H05K1/181 ,  H05K7/1432 ,  H05K7/20854 ,  H05K2201/09972

Abstract: In an electronic control unit, high-heat-generating devices are mounted on a first surface or a second surface of a board, a heat-dissipating member is located facing the first surface of the board, and a heat-conducting member is located between the board and the heat-dissipating member. The heat-conducting member is in contact with the high-heat-generating devices to transfer heat of the high-heat-generating devices to the heat-dissipating member. A ratio of the number of the high-heat-generating devices mounted on the board to the number of the high-heat-generating devices arranged inside a first limited region of the first surface or a second limited region of the second surface is greater than a predetermined ratio. The second limited region is located at a position corresponding to the first limited region.

Abstract translation: 在电子控制单元中，高温发生装置安装在板的第一表面或第二表面上，散热构件面向板的第一表面定位，并且导热构件位于 板和散热构件。 导热构件与高发热装置接触，以将高发热装置的热传递到散热构件。 安装在板上的高发热装置的数量与布置在第一表面的第一有限区域内的高发热装置的数量或第二表面的第二限制区域的数量的比率大于 预定比例。 第二有限区域位于与第一有限区域对应的位置。

公开(公告)号：US09063176B2

公开(公告)日：2015-06-23

申请号：US13106730

申请日：2011-05-12

Applicant: Iain Barnett ,  William Michael James Holland ,  Jonathan Ephraim David Hurwitz

Inventor： Iain Barnett ,  William Michael James Holland ,  Jonathan Ephraim David Hurwitz

IPC: H03K5/153 ,  G01R19/12 ,  G01R15/16 ,  G01R15/06

CPC classification number: H05K1/162 ,  G01R15/06 ,  G01R15/16 ,  G01R19/12 ,  G01R19/175 ,  H03H7/004 ,  H05K1/0239 ,  H05K1/0256 ,  H05K2201/09309 ,  H05K2201/09972

Abstract: A signal level crossing detector circuit includes a DC isolator and a detector circuit. The DC isolator has at least a first input, which is operable to receive a high voltage AC signal, and at least a first capacitor, a first plate of the first capacitor being electrically connected to the first input. The detector circuit is operable at a low voltage and has at least a first detector input, the first detector input being electrically connected to a second plate of the first capacitor, the low voltage detector circuit being operable to provide a change in output signal in dependence on a high voltage AC signal on the first input crossing a predetermined signal level. The signal level crossing detector may be single ended or differential.

Abstract translation: 信号电平交叉检测器电路包括直流隔离器和检测器电路。 DC隔离器具有至少第一输入，其可操作以接收高压AC信号，以及至少第一电容器，第一电容器的第一板电连接到第一输入端。 检测器电路可在低电压下操作并且具有至少第一检测器输入，第一检测器输入电连接到第一电容器的第二板，低电压检测器电路可操作以依次提供输出信号的变化 在第一输入端上的高电压AC信号上穿过预定的信号电平。 信号电平交叉检测器可以是单端或差分。