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    Prediction and control of NBTI of integrated circuits
    166.
    发明授权
    Prediction and control of NBTI of integrated circuits 有权
    集成电路NBTI的预测与控制

    公开(公告)号：US08050901B2

    公开(公告)日：2011-11-01

    申请号：US11800623

    申请日：2007-05-07

    Applicant: Jing-Cheng Lin

    Inventor： Jing-Cheng Lin

    IPC: G06F17/50

    CPC classification number: G06F17/5036

    Abstract: A modeling system for modeling integrated circuits includes a process variation generator for generating a first statistic distribution of a process parameter; a performance parameter distribution generator for generating a second distribution of a performance parameter; a stress generator for generating a third statistic distribution of the performance parameter under a stress condition; and a circuit simulator for receiving data randomly generated based on the first, the second and the third distributions and for generating a statistic distribution of a target performance parameter.

    Abstract translation: 用于对集成电路进行建模的建模系统包括用于生成过程参数的第一统计分布的过程变化发生器; 性能参数分配生成器，用于生成性能参数的第二分布; 应力发生器，用于在应力条件下产生所述性能参数的第三统计分布; 以及电路模拟器，用于接收基于第一，第二和第三分布随机生成的数据，并用于生成目标性能参数的统计分布。

    Method for forming composite barrier layer
    167.
    发明授权
    Method for forming composite barrier layer 有权
    形成复合阻挡层的方法

    公开(公告)号：US08034709B2

    公开(公告)日：2011-10-11

    申请号：US12287516

    申请日：2008-10-10

    Applicant: Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

    Inventor： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

    IPC: H01L21/4763

    CPC classification number: H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  Y10S438/927

    Abstract: Provided is a method for forming a composite barrier layer with superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer generally form boundaries with dielectric materials and crystalline layers generally form boundaries with conductive materials such as interconnect materials.

    Abstract translation: 提供了一种形成复合阻挡层的方法，该复合阻挡层具有优异的阻挡性能，并且当复合阻挡层贯穿整个半导体器件时，两种介电材料和导电材料具有优异的粘合性能。 复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。 复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。 复合阻挡层的非晶层通常与电介质材料形成边界，并且结晶层通常与诸如互连材料的导电材料形成边界。

    Germanium Field Effect Transistors and Fabrication Thereof
    169.
    发明申请
    Germanium Field Effect Transistors and Fabrication Thereof 有权
    锗场效应晶体管及其制作

    公开(公告)号：US20100237444A1

    公开(公告)日：2010-09-23

    申请号：US12630652

    申请日：2009-12-03

    Applicant: Jing-Cheng Lin

    Inventor： Jing-Cheng Lin

    IPC: H01L29/78 ,  H01L21/28

    CPC classification number: H01L29/7833 ,  H01L21/02175 ,  H01L21/28255 ,  H01L29/16 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659

    Abstract: Germanium field effect transistors and methods of fabricating them are described. In one embodiment, the method includes forming a germanium oxide layer over a substrate and forming a metal oxide layer over the germanium oxide layer. The germanium oxide layer and the metal oxide layer are converted into a first dielectric layer. A first electrode layer is deposited over the first dielectric layer.

    Abstract translation: 描述锗场效应晶体管及其制造方法。 在一个实施例中，该方法包括在衬底上形成氧化锗层并在氧化锗层上形成金属氧化物层。 氧化锗层和金属氧化物层被转换为第一电介质层。 第一电极层沉积在第一介电层上。

    N-FET with a Highly Doped Source/Drain and Strain Booster
    170.
    发明申请
    N-FET with a Highly Doped Source/Drain and Strain Booster 有权
    具有高掺杂源/漏极和应变增强器的N-FET

    公开(公告)号：US20100155790A1

    公开(公告)日：2010-06-24

    申请号：US12341674

    申请日：2008-12-22

    Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

    Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L21/28255 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/7833

    Abstract: A structure and method of making an N-FET with a highly doped source/drain and strain booster are presented. The method provides a substrate with a Ge channel region. A gate dielectric is formed over the Ge channel and a gate electrode is formed over the gate dielectric. Sacrificial gate spacers are disposed on the sidewalls of the gate dielectric and gate electrode. Cavities are etched into the substrate extending under the sacrificial gate spacers. Si1−xGex source/drain regions are doped in-situ during formation, x

    Abstract translation: 提出了制造具有高掺杂源/漏和应变增强器的N-FET的结构和方法。 该方法提供具有Ge沟道区的衬底。 在Ge沟道上方形成栅极电介质，在栅极电介质上形成栅电极。 牺牲栅间隔件设置在栅极电介质和栅电极的侧壁上。 凹坑被蚀刻到在牺牲栅极间隔物下面延伸的衬底中。 Si1-xGex源/漏区在形成期间原位掺杂，x <0.85。

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