公开(公告)号：US20060128072A1

公开(公告)日：2006-06-15

申请号：US11011459

申请日：2004-12-13

申请人： Sarathy Rajagopalan ,  Kishor Desai ,  Shirish Shah

发明人： Sarathy Rajagopalan ,  Kishor Desai ,  Shirish Shah

IPC分类号： H01L21/82

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse formed in an integrated circuit die includes: a length of an electrically conductive material for connecting two points of a circuit on the integrated circuit die and for selectively breaking the connection by a pulse of electrical current sufficient to dissolve a portion of the electrically conductive material; a passivation layer formed over the length of electrically conductive material; and a protective coating formed over a portion of the length of electrically conductive material in addition to the passivation layer to avoid damage to the fuse from an etchant during a bumping process.

摘要翻译： 形成在集成电路管芯中的保险丝包括：用于连接集成电路管芯上的电路的两个点的导电材料的长度，并且用于通过足以溶解导电的一部分的电流的脉冲来选择性地断开连接 材料; 形成在导电材料的长度上的钝化层; 以及除了钝化层之外还在导电材料长度的一部分上形成的保护涂层，以避免在碰撞过程中从蚀刻剂损坏保险丝。

公开(公告)号：US07041516B2

公开(公告)日：2006-05-09

申请号：US10268361

申请日：2002-10-10

申请人： Sarathy Rajagopalan ,  Kishor Desai ,  John P. McCormick ,  Maniam Alagaratnam

发明人： Sarathy Rajagopalan ,  Kishor Desai ,  John P. McCormick ,  Maniam Alagaratnam

IPC分类号： H01L21/50 ,  G01R31/26

CPC分类号： H01L25/50 ,  H01L22/20 ,  H01L23/5385 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2224/0401

摘要： A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. The second integrated circuit is attached and electrically connected to a second substrate to form a second assembly, which is also tested to ensure that it functions properly. The first assembly is attached and electrically connected to the second assembly to form the multi chip module.

摘要翻译： 一种将至少第一集成电路和第二集成电路组装到多芯片模块中的方法。 第一集成电路被附接并电连接到第一基板以形成第一组件，其被测试以确保其正常工作。 第二集成电路被连接并电连接到第二基板以形成第二组件，其也被测试以确保其正常工作。 第一组件被附接并电连接到第二组件以形成多芯片模块。

公开(公告)号：US6133064A

公开(公告)日：2000-10-17

申请号：US322064

申请日：1999-05-27

申请人： Kumar Nagarajan ,  Kishor Desai

发明人： Kumar Nagarajan ,  Kishor Desai

IPC分类号： H01L21/56 ,  H01L23/42 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/42 ,  H01L21/563 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/16195

摘要： Methods and apparatus pertaining to flip chip ball grid array packages are disclosed. A substrate comprises a base layer with a dielectric laminated thereon such that a cavity in the dielectric exposes the base layer. A die is then mounted to the exposed portion of the base layer. Preferably, an upper portion of the dielectric forms a frame for receiving a heat spreader.

摘要翻译： 公开了与倒装芯片球栅阵列封装相关的方法和装置。 衬底包括其上具有电介质的基底层，使得电介质中的空腔暴露于基底层。 然后将模具安装到基层的暴露部分。 优选地，电介质的上部形成用于接收散热器的框架。

公开(公告)号：US08803269B2

公开(公告)日：2014-08-12

申请号：US13463408

申请日：2012-05-03

申请人： Kalpendu Shastri ,  Vipulkumar Patel ,  Mark Webster ,  Prakash Gothoskar ,  Ravinder Kachru ,  Soham Pathak ,  Rao V. Yelamarty ,  Thomas Daugherty ,  Bipin Dama ,  Kaushik Patel ,  Kishor Desai

发明人： Kalpendu Shastri ,  Vipulkumar Patel ,  Mark Webster ,  Prakash Gothoskar ,  Ravinder Kachru ,  Soham Pathak ,  Rao V. Yelamarty ,  Thomas Daugherty ,  Bipin Dama ,  Kaushik Patel ,  Kishor Desai

IPC分类号： H01L31/0232 ,  H01L29/40 ,  H01L23/053 ,  H01L23/12

CPC分类号： H01L25/50 ,  G02B6/423 ,  G02B6/4244 ,  G02B6/4245 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/426 ,  H01L25/167 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

摘要： A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.

摘要翻译： 光电子收发器组件过程的晶片级实现利用硅晶片作为光学参考平面和平台，同时为多个单独的收发器模块组装所有必需的光学和电子部件。 特别地，硅晶片被用作“平台”（插入器），在其上安装或集成多个收发器模块的所有组件，硅插入器的顶表面用作参考平面，用于定义 分离光学元件之间的光信号路径。 实际上，通过使用单个硅晶片作为大量单独的收发器模块的平台，可以使用晶片尺度组装过程以及这些模块的光学对准和测试。

公开(公告)号：US08525312B2

公开(公告)日：2013-09-03

申请号：US13208822

申请日：2011-08-12

申请人： Qwai H. Low ,  Chok J. Chia ,  Kishor Desai ,  Charles G. Woychik ,  Huailiang Wei

发明人： Qwai H. Low ,  Chok J. Chia ,  Kishor Desai ,  Charles G. Woychik ,  Huailiang Wei

IPC分类号： H01L23/495 ,  H01L21/50 ,  H01L21/60

CPC分类号： H01L23/49537 ,  H01L21/4821 ,  H01L23/3121 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83

摘要： A microelectronic assembly can include a microelectronic element and a lead frame having a first unit and a second unit overlying the first unit and assembled therewith. The first unit can have a first metal layer comprising a portion of the thickness of the lead frame and including terminals and first conductive elements extending away therefrom. The second unit can have a second metal layer comprising a portion of the thickness of the lead frame and including bond pads and second conductive elements extending away therefrom. The first and second units each can have an encapsulation supporting at least portions of the respective first and second conductive elements. At least some of the second conductive elements can overlie portions of corresponding ones of the first conductive elements and can be joined thereto. The microelectronic element can have contacts electrically connected with the bond pads of the lead frame.

摘要翻译： 微电子组件可以包括微电子元件和引线框架，引线框架具有覆盖第一单元并与其组装的第一单元和第二单元。 第一单元可以具有包括引线框架的厚度的一部分的第一金属层，并且包括端子和从其延伸的第一导电元件。 第二单元可以具有包括引线框架的厚度的一部分的第二金属层，并且包括接合焊盘和从其延伸的第二导电元件。 第一和第二单元各自可以具有支撑相应的第一和第二导电元件的至少一部分的封装。 至少一些第二导电元件可以覆盖相应的第一导电元件的部分并且可以与其连接。 微电子元件可以具有与引线框架的接合焊盘电连接的触点。

公开(公告)号：US20130183008A1

公开(公告)日：2013-07-18

申请号：US13737080

申请日：2013-01-09

申请人： Kalpendu Shastri ,  Soham Pathak ,  Utpal Chakrabarti ,  Vipulkumar Patel ,  Bipin Dama ,  Ravinder Kachru ,  Kishor Desai

发明人： Kalpendu Shastri ,  Soham Pathak ,  Utpal Chakrabarti ,  Vipulkumar Patel ,  Bipin Dama ,  Ravinder Kachru ,  Kishor Desai

IPC分类号： G02B6/42

CPC分类号： G02B6/4292 ,  B82Y20/00 ,  C03C15/00 ,  G02B6/136 ,  G02B6/4214 ,  G02B6/4246 ,  G02B6/4259 ,  Y10T29/4978

摘要： An apparatus for providing self-aligned optical coupling between an opto-electronic substrate and a fiber array, where the substrate is enclosed by a transparent lid such that the associated optical signals enter and exit the arrangement through the transparent lid. The apparatus takes the form of a two-part connectorized fiber array assembly where the two pieces uniquely mate to form a self-aligned configuration. A first part, in the form of a plate, is attached to the transparent lid in the area where the optical signals pass through. The first plate includes a central opening with inwardly-tapering sidewalls surrounding its periphery. A second plate is also formed to include a central opening and has a lower protrusion with inwardly-tapering sidewalls that mate with the inwardly-tapering sidewalls of the first plate to form the self-aligned connectorized fiber array assembly. The fiber array is then attached to the second plate in a self-aligned fashion.

摘要翻译： 一种用于在光电子基板和光纤阵列之间提供自对准光耦合的装置，其中基板由透明盖包围，使得相关联的光信号通过透明盖进入和离开布置。 该装置采取两部分连接的光纤阵列组件的形式，其中两个部件独特地配合以形成自对准配置。 在光信号通过的区域中，透明盖附着有板的形式的第一部分。 第一板包括具有围绕其周边的向内逐渐变细的侧壁的中心开口。 第二板也形成为包括中心开口并且具有下突起，其具有向内渐缩的侧壁，与第一板的向内渐缩的侧壁配合形成自对准的连接纤维阵列组件。 然后将纤维阵列以自对准的方式附接到第二板。

公开(公告)号：US20130101250A1

公开(公告)日：2013-04-25

申请号：US13656528

申请日：2012-10-19

申请人： Kishor Desai ,  Ravinder Kachru ,  Vipulkumar Patel ,  Bipin Dama ,  Kalpendu Shastri ,  Soham Pathak

发明人： Kishor Desai ,  Ravinder Kachru ,  Vipulkumar Patel ,  Bipin Dama ,  Kalpendu Shastri ,  Soham Pathak

IPC分类号： G02B6/12 ,  H01L33/52

CPC分类号： G02B6/4255 ,  G02B6/12 ,  G02B6/13 ,  G02B6/4201 ,  G02B6/4257 ,  G02B6/4292 ,  G02B6/43 ,  H01L21/50 ,  H01L23/04 ,  H01L23/48 ,  H01L25/167 ,  H01L31/0203 ,  H01L33/52 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/1616 ,  H01L2924/165 ,  H01L2924/16788 ,  H05K1/0268 ,  H05K1/0274 ,  H05K2201/10121 ,  H01L2924/0105 ,  H01L2924/01079

摘要： An opto-electronic assembly is provided comprising a substrate (generally of silicon or glass) for supporting a plurality of interconnected optical and electrical components. A layer of sealing material is disposed to outline a defined peripheral area of the substrate. A molded glass lid is disposed over and bonded to the substrate, where the molded glass lid is configured to create a footprint that matches the defined peripheral area of the substrate. The bottom surface of the molded glass lid includes a layer of bonding material that contacts the substrate's layer of sealing material upon contact, creating a bonded assembly. In one form, a wafer level assembly process is proposed where multiple opto-electronic assemblies are disposed on a silicon wafer and multiple glass lids are molded in a single sheet of glass that is thereafter bonded to the silicon wafer.

摘要翻译： 提供了一种光电子组件，其包括用于支撑多个互连的光学和电气部件的基板（通常为硅或玻璃）。 设置一层密封材料以概述衬底的限定的周边区域。 将模制的玻璃盖设置在基底上并结合到基底上，其中模制的玻璃盖构造成产生与限定的基底周边区域匹配的覆盖区。 模制玻璃盖的底表面包括一层接合材料，其在接触时接触基底的密封材料层，形成结合组件。 在一种形式中，提出了一种晶片级组装工艺，其中多个光电组件设置在硅晶片上，并且多个玻璃盖被模制在一片玻璃中，然后将其粘合到硅晶片上。

公开(公告)号：US20130037925A1

公开(公告)日：2013-02-14

申请号：US13208822

申请日：2011-08-12

申请人： Qwai H. Low ,  Chok J. Chia ,  Kishor Desai ,  Charles G. Woychik ,  Huailiang Wei

发明人： Qwai H. Low ,  Chok J. Chia ,  Kishor Desai ,  Charles G. Woychik ,  Huailiang Wei

IPC分类号： H01L23/495 ,  H01L21/50 ,  H01L21/60

CPC分类号： H01L23/49537 ,  H01L21/4821 ,  H01L23/3121 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83

摘要： A microelectronic assembly can include a microelectronic element and a lead frame having a first unit and a second unit overlying the first unit and assembled therewith. The first unit can have a first metal layer comprising a portion of the thickness of the lead frame and including terminals and first conductive elements extending away therefrom. The second unit can have a second metal layer comprising a portion of the thickness of the lead frame and including bond pads and second conductive elements extending away therefrom. The first and second units each can have an encapsulation supporting at least portions of the respective first and second conductive elements. At least some of the second conductive elements can overlie portions of corresponding ones of the first conductive elements and can be joined thereto. The microelectronic element can have contacts electrically connected with the bond pads of the lead frame.

摘要翻译： 微电子组件可以包括微电子元件和引线框架，引线框架具有覆盖第一单元并与其组装的第一单元和第二单元。 第一单元可以具有包括引线框架的厚度的一部分的第一金属层，并且包括端子和从其延伸的第一导电元件。 第二单元可以具有包括引线框架的厚度的一部分的第二金属层，并且包括接合焊盘和从其延伸的第二导电元件。 第一和第二单元各自可以具有支撑相应的第一和第二导电元件的至少一部分的封装。 至少一些第二导电元件可以覆盖相应的第一导电元件的部分并且可以与其连接。 微电子元件可以具有与引线框架的接合焊盘电连接的触点。

公开(公告)号：US08723049B2

公开(公告)日：2014-05-13

申请号：US13156609

申请日：2011-06-09

申请人： Charles G. Woychik ,  Kishor Desai ,  Ilyas Mohammed ,  Terrence Caskey

发明人： Charles G. Woychik ,  Kishor Desai ,  Ilyas Mohammed ,  Terrence Caskey

IPC分类号： H05K1/11

CPC分类号： H05K3/0094 ,  B23K1/0016 ,  B23K35/24 ,  B23K35/36 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49883 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/07811 ,  H01L2924/09701 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The conductive via can include a plurality of base particles each including a first region of a first metal substantially covered by a layer of a second metal different from the first metal. The base particles can be metallurgically joined together and the second metal layers of the particles can be at least partially diffused into the first regions. The conductive via can include voids interspersed between the joined base particles. The voids can occupy 10% or more of a volume of the conductive via.

摘要翻译： 部件可以包括具有第一表面和远离其的第二表面的基板，沿着第一和第二表面之间的方向延伸的开口以及在开口内延伸的导电通孔。 基底可以具有小于10ppm /℃的CTE。导电通孔可以包括多个基础颗粒，每个基底颗粒包括基本上被不同于第一金属的第二金属层覆盖的第一金属的第一区域。 基础颗粒可以冶金学连接在一起，并且颗粒的第二金属层可以至少部分地扩散到第一区域中。 导电通孔可以包括散布在接合的基础颗粒之间的空隙。 空隙可以占据导电通孔体积的10％或更多。

公开(公告)号：US08525309B2

公开(公告)日：2013-09-03

申请号：US13173883

申请日：2011-06-30

申请人： Chok Chia ,  Qwai Low ,  Kishor Desai ,  Charles G. Woychik

发明人： Chok Chia ,  Qwai Low ,  Kishor Desai ,  Charles G. Woychik

IPC分类号： H01L23/495 ,  H01L21/50 ,  H01L23/34 ,  H01L21/60 ,  H01R43/16

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/11332 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13339 ,  H01L2224/13347 ,  H01L2224/1339 ,  H01L2224/13401 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81192 ,  H01L2224/8184 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/07811 ,  Y10T29/49204 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/00

摘要： A microelectronic unit can include a lead frame and a device chip. The lead frame can have a plurality of monolithic lead fingers extending in a plane of the lead frame. Each lead finger can have a fan-out portion and a chip connection portion extending in the lead frame plane. The fan-out portions can have first and second opposed surfaces and a first thickness in a first direction between the opposed surfaces. The chip connection portions can have a second thickness smaller than the first thickness. The chip connection portions can define a recess below the first surface. The device chip can have a plurality of at least one of passive devices or active devices. The device chip can have contacts thereon facing the chip connection portions and electrically coupled thereto. At least a portion of a thickness of the device chip can extend within the recess.

摘要翻译： 微电子单元可以包括引线框架和器件芯片。 引线框架可以具有在引线框架的平面中延伸的多个单片引线指。 每个引线指可以具有在引线框架平面中延伸的扇出部分和芯片连接部分。 扇出部分可以在相对的表面之间具有第一和第二相对表面以及在第一方向上的第一厚度。 芯片连接部分可以具有小于第一厚度的第二厚度。 芯片连接部分可以限定第一表面下方的凹陷。 器件芯片可以具有多个无源器件或有源器件中的至少一个。 器件芯片可以具有面向芯片连接部分并且与其电耦合的触点。 装置芯片的厚度的至少一部分可以在凹部内延伸。