公开(公告)号：US20050206012A1

公开(公告)日：2005-09-22

申请号：US10801205

申请日：2004-03-16

Applicant: Warren Farnworth ,  William Hiatt ,  Tim Murphy ,  John Caldwell ,  Michael Slaughter ,  David Hembree ,  Jamie Wanke

Inventor： Warren Farnworth ,  William Hiatt ,  Tim Murphy ,  John Caldwell ,  Michael Slaughter ,  David Hembree ,  Jamie Wanke

IPC: H01L21/56 ,  H01L23/48 ,  H01L23/485

CPC classification number: H01L24/06 ,  H01L21/563 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2224/45099

Abstract: Stress and force management techniques for a semiconductor die to help compensate for stress within the semiconductor die and to help compensate for forces applied to the semiconductor die to minimize damage thereto.

Abstract translation: 用于半导体管芯的应力和力管理技术来帮助补偿半导体管芯内的应力，并帮助补偿施加到半导体管芯上的力以最小化对其的损害。

公开(公告)号：US20050064681A1

公开(公告)日：2005-03-24

申请号：US10666742

申请日：2003-09-19

Applicant: Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

Inventor： Alan Wood ,  Warren Farnworth ,  David Hembree ,  Sidney Rigg ,  William Hiatt ,  Peter Benson ,  Kyle Kirby ,  Salman Akram

IPC: E21B43/02 ,  G03F7/00 ,  G03F7/004 ,  H01L21/30 ,  H01L21/46

CPC classification number: G03F7/0037 ,  B33Y30/00 ,  B33Y70/00 ,  B33Y80/00 ,  G03F7/0047

Abstract: A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion which extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member which substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface. Assemblies that include the support structure and a semiconductor substrate are also within the scope of the present invention, as are methods for forming the support structures and thinning and post-thinning processes that include use of the support structures.

Abstract translation: 在半导体衬底的薄化或后研磨以及后稀化处理期间与半导体衬底一起使用的支撑结构包括基本上沿半导体衬底的外周延伸并且围绕半导体衬底的外周延伸的部分，以使薄化半导体 基板具有刚性。 支撑结构可以被配置为环或作为基本上覆盖半导体衬底的有源表面并且在由有源表面承载的每个半导体器件上形成保护结构的构件。 包括支撑结构和半导体衬底的组件也在本发明的范围内，形成支撑结构的方法和包括使用支撑结构的减薄和后变薄工艺也是如此。

公开(公告)号：US06365967B1

公开(公告)日：2002-04-02

申请号：US09318280

申请日：1999-05-25

Applicant: Salman Akram ,  David Hembree

Inventor： Salman Akram ,  David Hembree

IPC: H01L2348

CPC classification number: H01L24/02 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/10165 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/8014 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  Y10T29/49 ,  H01L2924/00

Abstract: A method for forming an interconnect structure includes providing a substrate, and forming a raised contact member on the substrate. A conductive layer is formed covering at least a portion of the raised contact member. A conductive trace is formed on the substrate in electrical communication with the conductive layer, and an alignment grid is formed on the substrate proximate the raised contact member. An interconnect structure includes a substrate and a raised contact member defined in the substrate. A conductive layer covers at least a portion of the raised contact member, and a conductive trace is in electrical communication with the conductive layer. An alignment grid is proximate the raised contact member.

Abstract translation: 形成互连结构的方法包括提供衬底，以及在衬底上形成凸起的接触构件。 形成覆盖凸起接触构件的至少一部分的导电层。 导电迹线形成在与导电层电连通的衬底上，并且在靠近凸起的接触构件的衬底上形成对准栅极。 互连结构包括衬底和限定在衬底中的凸起接触构件。 导电层覆盖凸起接触构件的至少一部分，并且导电迹线与导电层电连通。 对准网格靠近凸起的接触构件。

公开(公告)号：US20070179654A1

公开(公告)日：2007-08-02

申请号：US11731488

申请日：2007-03-30

Applicant: William Hiatt ,  Warren Farnworth ,  David Hembree ,  Peter Benson

Inventor： William Hiatt ,  Warren Farnworth ,  David Hembree ,  Peter Benson

IPC: G06F19/00

CPC classification number: B29C64/35 ,  B29C64/135 ,  B33Y30/00 ,  B33Y40/00 ,  B33Y50/02

Abstract: A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one fabrication site. The at least one fabrication site may be configured to receive one or more fabrication substrates, such as semiconductor substrates. A machine vision system with a translatable or locationally fixed camera may be associated with the at least one fabrication site and the material consolidation system. A cleaning component may also be associated with the at least one fabrication site. The cleaning component may share one or more elements with the at least one fabrication site, or may be separate therefrom. The programmed material consolidation apparatus may also include a substrate handling system, which places fabrication substrates at appropriate locations of the programmed material consolidation apparatus.

公开(公告)号：US20070088451A1

公开(公告)日：2007-04-19

申请号：US11545067

申请日：2006-10-06

Applicant: Salman Akram ,  Warren Farnworth ,  Derek Gouchnour ,  David Hembree ,  Michael Hess ,  John Jacobson ,  James Wark ,  Alan Wood

Inventor： Salman Akram ,  Warren Farnworth ,  Derek Gouchnour ,  David Hembree ,  Michael Hess ,  John Jacobson ,  James Wark ,  Alan Wood

IPC: G06F19/00

CPC classification number: G03F7/7065 ,  G06F11/006 ,  H01L2223/5444

Abstract: An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on ICs at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the ICs. The ID codes of the ICs are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the ICs is then accessed, and additional repair procedures the ICs may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.

Abstract translation: 在集成电路（IC）制造过程中的创造性方法，用于使用关于在探针上的IC进行的修复程序的数据，以确定是否在制造过程中稍后进行进一步的修理，包括将数据与每个的熔丝ID相关联地存储 IC。 IC的ID代码在制造过程中例如在打开/短路测试中自动读取。 然后访问与IC的ID代码相关联存储的数据，并且根据所访问的数据选择IC可能经历的附加修复过程。 因此，例如，访问的数据可以指示IC不可修复，因此IC可以直接进入废料仓，而不必被查询以确定其是否可修复，如在传统IC制造过程中所必需的。

公开(公告)号：US20060261340A1

公开(公告)日：2006-11-23

申请号：US11494453

申请日：2006-07-28

Applicant: Warren Farnworth ,  Sidney Rigg ,  William Hiatt ,  Kyle Kirby ,  Peter Benson ,  James Wark ,  Alan Wood ,  David Hembree ,  Salman Akram ,  Charles Watkins

Inventor： Warren Farnworth ,  Sidney Rigg ,  William Hiatt ,  Kyle Kirby ,  Peter Benson ,  James Wark ,  Alan Wood ,  David Hembree ,  Salman Akram ,  Charles Watkins

IPC: H01L29/04 ,  H01L33/00 ,  H01L29/768 ,  H01L27/148 ,  H01L31/0203

CPC classification number: H01L27/14618 ,  H01L23/481 ,  H01L24/48 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the die and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad with conductive fill material at least partially disposed in the passage. An electrically conductive support member is carried by and projects from the bond-pad. A cover over the image sensor is coupled to the support member.

Abstract translation: 本文公开了微电子成像器和用于封装微电子成像器的方法。 在一个实施例中，微电子成像单元可以包括微电子管芯，图像传感器，电耦合到图像传感器的集成电路以及电耦合到集成电路的接合焊盘。 导电晶片互连延伸穿过管芯并且与焊盘接触。 互连可以包括完全延伸穿过基底的通道和具有至少部分地设置在通道中的导电填充材料的接合垫。 导电支撑构件由接合垫承载和突出。 图像传感器上的盖连接到支撑构件。

公开(公告)号：US20060113682A1

公开(公告)日：2006-06-01

申请号：US11333662

申请日：2006-01-17

Applicant: Warren Farnworth ,  Alan Wood ,  William Hiatt ,  James Wark ,  David Hembree ,  Kyle Kirby ,  Pete Benson

Inventor： Warren Farnworth ,  Alan Wood ,  William Hiatt ,  James Wark ,  David Hembree ,  Kyle Kirby ,  Pete Benson

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/04

CPC classification number: H01L21/561 ,  B33Y70/00 ,  B33Y80/00 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05178 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/207 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.

Abstract translation: 半导体部件包括基模和层叠在基模上的二次模。 基模具包括形成用于部件的内部信号传输系统的导电通孔，并允许二次管芯的电路侧接合到基座的后侧。 该组件还包括与导电通孔电连通的基座芯片的电路侧上的端子触点阵列。 该组件还可以包括在基模的背侧上的密封剂，其基本上封装次模，以及在用作保护层的基模的电路侧上的聚合物层，用于形成的用于固化的模板 终端接触。 一种用于制造该部件的方法包括将单个二次骰子接合到基底晶片上的基底骰子上，或将次晶片接合到基底晶片，或将单个二次骰子接合到单个基体骰子的步骤。

公开(公告)号：US20060081583A1

公开(公告)日：2006-04-20

申请号：US11265610

申请日：2005-11-02

Applicant: David Hembree ,  Warren Farnworth

Inventor： David Hembree ,  Warren Farnworth

IPC: H05B3/00 ,  H05B1/00 ,  H05B11/00

CPC classification number: B23K1/0053 ,  B23K1/012 ,  B23K2101/40 ,  G01R1/0483 ,  G01R31/2863 ,  G01R31/2886 ,  H01L22/32 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13111 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81052 ,  H01L2224/81201 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K3/325 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2203/081 ,  H05K2203/111 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method for enhancing temporary solder ball connection comprises the application of thermal energy to the solder balls, heating them to a submelting “softening” temperature, whereby the compression force required to connect all balls in a BGA is achieved at much reduced force, avoiding damage to the package, insert, substrate and support apparatus. Several forms of heating apparatus, and temperature measuring apparatus are disclosed.

公开(公告)号：US20050275084A1

公开(公告)日：2005-12-15

申请号：US11152513

申请日：2005-06-14

Applicant: Kyle Kirby ,  Warren Farnworth ,  James Wark ,  William Hiatt ,  David Hembree ,  Alan Wood

Inventor： Kyle Kirby ,  Warren Farnworth ,  James Wark ,  William Hiatt ,  David Hembree ,  Alan Wood

IPC: G01R1/073 ,  H01L21/66 ,  H01L23/48 ,  H01L23/498 ,  H01L23/58 ,  H01R13/24 ,  H05K3/32 ,  H05K3/40 ,  H05K7/06 ,  H05K7/10

CPC classification number: G01R1/0735 ,  G01R1/07314 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01R12/714 ,  H01R13/24 ,  H01R2201/20 ,  H05K3/326 ,  H05K7/1069 ,  H05K2201/0314 ,  H05K2201/09036 ,  H05K2201/10378 ,  Y10T29/49165 ,  Y10T29/49174 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2224/05599

Abstract: A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension within the substrate results in a compliant deflection orthogonal to the plane of the substrate. The contact pin assembly is formed by generally thinning the substrate around the contact pin location and then specifically thinning the substrate immediately around the contact pin location for forming a void. The contact pin is compliantly coupled, in one embodiment by compliant coupling material, and in another embodiment by compliantly flexible portions of the substrate.

Abstract translation: 提供了柔性接触销组件和接触器卡系统。 柔性接触销组件包括由基板的一部分形成的接触销，其中触头销顺从地保持通过柔性联接结构悬挂在基板内。 衬底内的悬浮液导致与衬底的平面垂直的柔顺偏转。 接触销组件通过使基板围绕接触销位置大体变薄而形成，然后特别地使基板在接触销位置周围特别地变薄以形成空隙。 在一个实施例中，接触销被顺从地联接，在一个实施例中通过柔性耦合材料，并且在另一个实施例中，通过柔性柔性部分的衬底。

公开(公告)号：US20050275051A1

公开(公告)日：2005-12-15

申请号：US10867505

申请日：2004-06-14

Applicant: Warren Farnworth ,  Sidney Rigg ,  David Hembree ,  William Hiatt

Inventor： Warren Farnworth ,  Sidney Rigg ,  David Hembree ,  William Hiatt

IPC: H01L27/146 ,  H01L27/148 ,  H01L31/0203

CPC classification number: H01L31/0203 ,  B33Y80/00 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14689 ,  H01L27/148 ,  H01L2224/48227 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: Microelectronic imagers with prefabricated housings and methods of packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imager can include a microelectronic die, an image sensor, and an integrated circuit operatively coupled to the integrated circuit. The microelectronic imager also includes an optic unit having an optic member. The microelectronic imager further includes a prefabricated housing having a first mounting site and a second mounting site. The die is seated within the housing at the first mounting site and the optics unit is seated within the housing at the second mounting site in a fixed, preset position in which the optic member is situated at a desired location relative to the image sensor.

Abstract translation: 具有预制外壳的微电子成像器和封装微电子成像器的方法在此公开。 在一个实施例中，微电子成像器可以包括微电子管芯，图像传感器和可操作地耦合到集成电路的集成电路。 微电子成像器还包括具有光学构件的光学单元。 微电子成像器还包括具有第一安装位置和第二安装位置的预制外壳。 模具位于第一安装位置的壳体内，并且光学单元在第二安装位置处置于壳体内的固定的预设位置中，光学构件位于相对于图像传感器的期望位置处。