公开(公告)号：US08575760B2

公开(公告)日：2013-11-05

申请号：US13303255

申请日：2011-11-23

Applicant: Jae-hyun Phee ,  Uihyouong Lee ,  Ju-il Choi ,  Jung-Hwan Kim

Inventor： Jae-hyun Phee ,  Uihyouong Lee ,  Ju-il Choi ,  Jung-Hwan Kim

IPC: H01L23/498

CPC classification number: H01L29/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05571 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13076 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a substrate having a first surface and an opposite second surface. An electrode extends within the substrate towards the first surface and has a protruding portion extending from the first surface. A supporting portion extends from the first surface of the substrate to a sidewall of the protruding portion and supports the protruding portion.

Abstract translation: 半导体器件包括具有第一表面和相对的第二表面的衬底。 电极在衬底内朝向第一表面延伸并且具有从第一表面延伸的突出部分。 支撑部分从基板的第一表面延伸到突出部分的侧壁并支撑突出部分。

公开(公告)号：US08564102B2

公开(公告)日：2013-10-22

申请号：US13108231

申请日：2011-05-16

Applicant: Ju-il Choi ,  Jae-hyun Phee ,  Kyu-ha Lee ,  Ho-jin Lee ,  Son-kwan Hwang

Inventor： Ju-il Choi ,  Jae-hyun Phee ,  Kyu-ha Lee ,  Ho-jin Lee ,  Son-kwan Hwang

IPC: H01L29/40 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76879 ,  H01L21/76844 ,  H01L21/76873 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/05009 ,  H01L2224/06181

Abstract: A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an interlayer insulation layer pattern, a metal wire pattern exposed by a passage formed by a via hole formed in the interlayer insulation layer pattern to input and output an electrical signal, and a plated layer pattern directly contacting the metal wire pattern and filling the via hole. The method includes forming an interlayer insulation layer having a metal wire pattern to input and output an electrical signal formed therein, forming a via hole to define a passage that extends through the interlayer insulation layer until at least a part of the metal wire pattern is exposed, and forming a plated layer pattern to fill the via hole and to directly contact the metal wire pattern by using the metal wire pattern exposed through the via hole as a seed metal layer.

Abstract translation: 半导体器件和半导体器件的制造方法。 半导体器件包括层间绝缘层图案，由形成在层间绝缘层图案中的通孔形成的通道暴露的金属线图案，以输入和输出电信号，以及直接接触金属线图案的镀层图案和 填充通孔。 该方法包括形成具有金属线图案的层间绝缘层，以输入和输出其中形成的电信号，形成通孔以限定延伸穿过层间绝缘层的通道，直到金属线图案的至少一部分露出 并且形成镀层图案以填充通孔并且通过使用通过通孔露出的金属线图案作为种子金属层直接接触金属线图案。

公开(公告)号：US20090305502A1

公开(公告)日：2009-12-10

申请号：US12476793

申请日：2009-06-02

Applicant: Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

Inventor： Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

IPC: H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract translation: 形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。 第一侧壁间隔层形成在互连孔的侧壁上。 在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。 该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。 然后用通孔电极填充互连孔和未切割的凹部。 去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。

公开(公告)号：US20080141933A1

公开(公告)日：2008-06-19

申请号：US11984402

申请日：2007-11-16

Applicant: Cha-jea Jo ,  Joong-hyun Baek ,  Hee-jin Lee ,  Ku-young Kim ,  Ju-il Choi

Inventor： Cha-jea Jo ,  Joong-hyun Baek ,  Hee-jin Lee ,  Ku-young Kim ,  Ju-il Choi

IPC: B05C5/00

CPC classification number: C25D5/08 ,  C25D7/123 ,  C25D17/001 ,  C25D21/10 ,  H01L21/2885

Abstract: Provided is a semiconductor plating system for plating a semiconductor object with a desired layer. The semiconductor plating system include a plating tank configured to accommodate a plating solution for use in plating the semiconductor object, and a plating solution induction device configured to induce the plating solution to spirally flow toward the semiconductor object.

Abstract translation: 提供了一种用于对具有期望层的半导体物体进行电镀的半导体电镀系统。 半导体电镀系统包括：电镀槽，其配置为容纳用于电镀半导体物体的电镀液;以及电镀液感应装置，其被配置为使电镀液向半导体物体螺旋状流动。

公开(公告)号：US20070176240A1

公开(公告)日：2007-08-02

申请号：US11556931

申请日：2006-11-06

Applicant: Hyun-soo Chung ,  Seung-duk Baek ,  Ju-il Choi ,  Dong-ho Lee

Inventor： Hyun-soo Chung ,  Seung-duk Baek ,  Ju-il Choi ,  Dong-ho Lee

IPC: H01L23/62

CPC classification number: H01L24/11 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/12 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/4813 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of forming a wire structure connecting to a bonding pad of a semiconductor chip includes depositing a passivation layer on an active surface of the semiconductor chip, depositing a seed metal layer on the bonding pad and the passivation layer, depositing a metal layer on the seed metal layer, etching selected portions of the seed metal layer, leaving unetched a first area, overlapping the bonding pad and a second area overlapping a connection pad, wherein the wire structure is formed by the metal layer being electrically connected to the bonding pad and the connection pad, but floating from the passivation layer, and depositing an insulting layer on the wire structure.

Abstract translation: 形成连接到半导体芯片的焊盘的导线结构的方法包括在半导体芯片的有源表面上沉积钝化层，在焊盘和钝化层上沉积种子金属层，在金属层上沉积金属层 种子金属层，蚀刻种子金属层的选定部分，留下未蚀刻的第一区域，与接合焊盘重叠，第二区域与连接焊盘重叠，其中线结构由金属层电连接到接合焊盘， 连接焊盘，但是从钝化层浮起，并且在导线结构上沉积绝缘层。

公开(公告)号：US10128168B2

公开(公告)日：2018-11-13

申请号：US14543688

申请日：2014-11-17

Applicant: Ju-il Choi ,  Kun-sang Park ,  Son-kwan Hwang ,  Ji-soon Park ,  Byung-lyul Park

Inventor： Ju-il Choi ,  Kun-sang Park ,  Son-kwan Hwang ,  Ji-soon Park ,  Byung-lyul Park

IPC: H01L23/532 ,  H01L23/48 ,  H01L23/31 ,  H01L25/065 ,  H01L21/768

Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer. The conductive barrier layer may include an outer portion oxidized between the conductive barrier layer and the via insulating layer, and the oxidized outer portion of the conductive barrier layer may substantially surrounds the remaining portion of the conductive barrier layer.

公开(公告)号：US20170148753A1

公开(公告)日：2017-05-25

申请号：US15345614

申请日：2016-11-08

Applicant: Ju-il Choi ,  Hyoju KIM ,  Byunglyul PARK ,  Yeun-Sang PARK ,  Jubin SEO ,  Atsushi FUJISAKI

Inventor： Ju-il Choi ,  Hyoju KIM ,  Byunglyul PARK ,  Yeun-Sang PARK ,  Jubin SEO ,  Atsushi FUJISAKI

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13076 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13211 ,  H01L2224/13239 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2224/1146 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/01029

Abstract: According to aspects provided herein, a semiconductor device may include a bump providing improved reliability and reduced size. In some aspects, a conductive pad may be formed on a substrate, and a conductive support layer, which may be a pillar, may be formed on the conductive pad. An intermetallic compound (IMC) layer may be formed on the conductive support layer, and a solder layer may be formed on the IMC layer. In some aspects, the conductive support layer may be of a smaller width than the IMC layer. In some aspects, the conductive support layer may have side surfaces which are wider at the solder side than at the conductive pad side. In some aspects, other layers may be formed, such as a seed layer between the conductive pad and the conductive support layer, or a barrier layer between the conductive support layer and the IMC layer.

公开(公告)号：US09219035B2

公开(公告)日：2015-12-22

申请号：US14153478

申请日：2014-01-13

Applicant: Ho-jin Lee ,  Kang-wook Lee ,  Myeong-soon Park ,  Ju-il Choi ,  Son-kwan Hwang

Inventor： Ho-jin Lee ,  Kang-wook Lee ,  Myeong-soon Park ,  Ju-il Choi ,  Son-kwan Hwang

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract translation: 形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。 第一侧壁间隔层形成在互连孔的侧壁上。 在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。 该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。 然后用通孔电极填充互连孔和未切割凹部。 去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。

公开(公告)号：US20120199981A1

公开(公告)日：2012-08-09

申请号：US13364678

申请日：2012-02-02

Applicant: Se-young Jeong ,  Ho-geon Song ,  Ju-il Choi ,  Jae-hyun Phee

Inventor： Se-young Jeong ,  Ho-geon Song ,  Ju-il Choi ,  Jae-hyun Phee

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/10135 ,  H01L2224/11015 ,  H01L2224/11464 ,  H01L2224/11622 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13171 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27436 ,  H01L2224/27622 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/81862 ,  H01L2224/81986 ,  H01L2224/83862 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/3511 ,  H01L2924/3651 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

Abstract translation: 半导体器件包括：第一器件，包括第一衬底和用于连接第一器件外部的第一外部连接端子; 堆叠在第一装置上的第二装置，第二装置包括第二基板和用于连接第二装置外部的第二外部连接端子; 布置在第一装置和第二装置之间的粘合剂图案，布置在除了设置第一外部连接端子和第二外部连接端子的位置以外的位置的粘合剂图案以及当堆叠时引起第一装置和第二装置的粘合剂图案， 间隔开预定距离; 以及设置在电气和物理上连接第一外部连接端子和第二外部连接端子之间的镀层。

公开(公告)号：US20110193229A1

公开(公告)日：2011-08-11

申请号：US13013290

申请日：2011-01-25

Applicant: Keum-Hee Ma ,  Woo-Dong Lee ,  Min-Seung Yoon ,  Ju-il Choi ,  Sang-Sick Park ,  Son-Kwan Hwang

Inventor： Keum-Hee Ma ,  Woo-Dong Lee ,  Min-Seung Yoon ,  Ju-il Choi ,  Sang-Sick Park ,  Son-Kwan Hwang

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L23/481 ,  H01L23/49816 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555

Abstract: A semiconductor device having semiconductor chips of different thicknesses is provided. The semiconductor device may include a first semiconductor chip, a sub-board on a first side of the first semiconductor chip, at least one second semiconductor chip on a second side of the first semiconductor chip, at least one external contact terminal on the at least one second semiconductor chip. In example embodiments the at least one second semiconductor chip may include a plurality of through silicon vias and the at least one external contact terminal may be in electrical contact with the first semiconductor chip and the at least one second semiconductor chip via the plurality of through silicon vias. In example embodiments, the at least one second semiconductor chip may be thinner than the first semiconductor chip.

Abstract translation: 提供具有不同厚度的半导体芯片的半导体器件。 半导体器件可以包括第一半导体芯片，在第一半导体芯片的第一侧上的子板，在第一半导体芯片的第二侧上的至少一个第二半导体芯片，至少一个外部接触端子 一秒钟的半导体芯片。 在示例实施例中，所述至少一个第二半导体芯片可以包括多个通孔硅通孔，并且所述至少一个外部接触端子可以经由多个通孔与第一半导体芯片和至少一个第二半导体芯片电接触 通孔 在示例实施例中，至少一个第二半导体芯片可以比第一半导体芯片更薄。