公开(公告)号：US20130344695A1

公开(公告)日：2013-12-26

申请号：US13966531

申请日：2013-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Chan Lim ,  Gilheyun Choi ,  Kwangjin Moon ,  Deok-Young Jung ,  Byung-Lyul Park ,  Dosun Lee

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/1147 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided are a semiconductor chip and a method of manufacturing the same. The semiconductor chip includes a substrate having a first side and a second side facing each other, and a through electrode being disposed in a hole penetrating the substrate, wherein an opening surrounded by the through electrode is disposed in the hole, wherein the opening comprises a first end adjacent to the first side of the substrate and a second end adjacent to the second side of the substrate

Abstract translation: 提供一种半导体芯片及其制造方法。 半导体芯片包括具有彼此相对的第一侧和第二侧的基板，以及设置在穿透基板的孔中的贯通电极，其中，由贯通电极包围的开口设置在孔中，其中，开口包括 与基板的第一侧相邻的第一端和与基板的第二侧相邻的第二端

公开(公告)号：US12014972B2

公开(公告)日：2024-06-18

申请号：US17403154

申请日：2021-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il Choi ,  Kwang-Jin Moon ,  Byung-Lyul Park ,  Jin-Ho An ,  Atsushi Fujisaki

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/14 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05155 ,  H01L2224/05546 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/10 ,  H01L2224/13023 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16111 ,  H01L2224/16112 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05611 ,  H01L2924/013 ,  H01L2924/01047 ,  H01L2224/03618 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a preliminary via structure through a portion of a substrate; partially removing the substrate to expose a portion of the preliminary via structure; forming a protection layer structure on the substrate to cover the portion of the preliminary via structure that is exposed; partially etching the protection layer structure to form a protection layer pattern structure and to partially expose the preliminary via structure; wet etching the preliminary via structure to form a via structure; and forming a pad structure on the via structure to have a flat top surface.

公开(公告)号：US20170033032A1

公开(公告)日：2017-02-02

申请号：US15163995

申请日：2016-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Hyung-Jun Jeon ,  Jum-Yong Park ,  Byung-Lyul Park ,  Ji-Soon Park ,  Jin-Ho An ,  Jin-Ho Chun

IPC: H01L23/48 ,  H01L21/78 ,  H01L23/532 ,  H01L21/768 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76852 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/31 ,  H01L23/3192 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/544 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2223/5446 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06151 ,  H01L2224/06156 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.

Abstract translation: 半导体器件包括具有管芯区域和围绕管芯区域的划线区域的衬底，穿过管芯区域中的衬底的多个通孔结构，一部分通孔结构暴露在衬底的表面上，以及 保护层图案结构，其设置在所述基板的表面上，所述表面包围所述通孔结构的所述暴露部分的侧壁，并且具有覆盖所述划线区域的与所述通孔结构相邻的至少一部分的突出部分。

公开(公告)号：US09490216B2

公开(公告)日：2016-11-08

申请号：US14596480

申请日：2015-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-Jin Moon ,  Tae-Seong Kim ,  Byung-Lyul Park ,  Jae-Hwa Park ,  Suk-Chul Bang

IPC: H01L23/522 ,  H01L23/544 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/544 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/522 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a semiconductor package. The semiconductor device includes semiconductor device includes a semiconductor substrate having a first side and a second side. A front-side structure including an internal circuit is disposed on the first side of the semiconductor substrate. A passivation layer is disposed on the second side of the semiconductor substrate. A through-via structure passes through the semiconductor substrate and the passivation layer. A back-side conductive pattern is disposed on the second side of the semiconductor substrate. The back-side conductive pattern is electrically connected to the through-via structure. An alignment recessed area is disposed in the passivation layer. An insulating alignment pattern is disposed in the alignment recessed area.

Abstract translation: 提供半导体器件和半导体封装。 半导体器件包括半导体器件，其包括具有第一侧和第二侧的半导体衬底。 包括内部电路的前侧结构设置在半导体衬底的第一侧上。 钝化层设置在半导体衬底的第二侧上。 通孔结构通过半导体衬底和钝化层。 背面导电图案设置在半导体衬底的第二侧上。 背面导电图案电连接到通孔结构。 在钝化层中设置对准凹陷区域。 绝缘对准图案设置在对准凹陷区域中。

公开(公告)号：US08860221B2

公开(公告)日：2014-10-14

申请号：US13685174

申请日：2012-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kun-Sang Park ,  Byung-Lyul Park ,  Su-Kyoung Kim ,  Kwang-Jin Moon ,  Suk-Chul Bang ,  Do-Sun Lee ,  Dong-Chan Lim ,  Gil-Heyun Choi

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/28 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0655 ,  H01L2224/05009 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/0903 ,  H01L2224/8001 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: Provided are electrode-connecting structures or semiconductor devices, including a lower device including a lower substrate, a lower insulating layer formed on the lower substrate, and a lower electrode structure formed in the lower insulating layer, wherein the lower electrode structure includes a lower electrode barrier layer and a lower metal electrode formed on the lower electrode barrier layer, and an upper device including an upper substrate, an upper insulating layer formed under the upper substrate, and an upper electrode structure formed in the upper insulating layer, wherein the upper electrode structure includes an upper electrode barrier layer extending from the inside of the upper insulating layer under a bottom surface thereof and an upper metal electrode formed on the upper electrode barrier layer. The lower metal electrode is in direct contact with the upper metal electrode.

Abstract translation: 提供了电极连接结构或半导体器件，包括下部器件，包括下部衬底，形成在下部衬底上的下部绝缘层和形成在下部绝缘层中的下部电极结构，其中下部电极结构包括下部电极 阻挡层和形成在下电极阻挡层上的下金属电极，以及上装置，包括上基板，形成在上基板下的上绝缘层和形成在上绝缘层中的上电极结构，上电极 结构包括从其下表面上的上绝缘层的内部延伸的上电极阻挡层和形成在上电极阻挡层上的上金属电极。 下部金属电极与上部金属电极直接接触。

公开(公告)号：US09728490B2

公开(公告)日：2017-08-08

申请号：US15151079

申请日：2016-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Hyo-Ju Kim ,  Yeun-Sang Park ,  Atsushi Fujisaki ,  Kwang-Jin Moon ,  Byung-Lyul Park

IPC: H01L23/485 ,  H01L23/48 ,  H01L23/31 ,  H01L23/532 ,  H01L23/29 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/481 ,  H01L21/486 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0501 ,  H01L2924/05032 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/10331 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a protection layer pattern structure provided on the surface of the substrate and including a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of the exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of the top surface of the first protection layer pattern adjacent to the sidewall of the via structure, and a pad structure provided on the via structure and the protection layer pattern structure and covering the top surface of the first protection layer pattern exposed by the second protection layer pattern.

公开(公告)号：US09653623B2

公开(公告)日：2017-05-16

申请号：US14956382

申请日：2015-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi-Koan Hong ,  Yeun-Sang Park ,  Byung-Lyul Park ,  Joo-Hee Jang

IPC: H01L31/02 ,  H01L31/0232 ,  H01L23/00

CPC classification number: H01L31/02005 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/91 ,  H01L31/02327 ,  H01L2224/04026 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06505 ,  H01L2224/06517 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/27416 ,  H01L2224/27602 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29014 ,  H01L2224/29022 ,  H01L2224/2929 ,  H01L2224/30051 ,  H01L2224/3013 ,  H01L2224/3014 ,  H01L2224/3015 ,  H01L2224/3016 ,  H01L2224/32147 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80903 ,  H01L2224/83193 ,  H01L2224/8388 ,  H01L2924/00014

Abstract: In a method for fabricating a semiconductor, a first conductive pattern structure partially protruding upwardly from first insulating interlayer is formed in first insulating interlayer. A first bonding insulation layer pattern covering the protruding portion of first conductive pattern structure is formed on first insulating interlayer. A first adhesive pattern containing a polymer is formed on first bonding insulation layer pattern to fill a first recess formed on first bonding insulation layer pattern. A second bonding insulation layer pattern covering the protruding portion of second conductive pattern structure is formed on second insulating interlayer. A second adhesive pattern containing a polymer is formed on second bonding insulation layer pattern to fill a second recess formed on second bonding insulation layer pattern. The first and second adhesive patterns are melted. The first and second substrates are bonded with each other so that the conductive pattern structures contact each other.

公开(公告)号：US09520361B2

公开(公告)日：2016-12-13

申请号：US14937406

申请日：2015-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Joo-Hee Jang ,  Jin-Ho Chun

IPC: H01L23/532 ,  H01L25/065

CPC classification number: H01L23/53228 ,  H01L21/76843 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L25/0657 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/08121 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive structure on the first conductive structure. The semiconductor device includes first and second metal-diffusion-blocking layers on respective sidewalls of the first and second conductive structures. The semiconductor device includes an insulating layer between the first and second metal-diffusion-blocking layers. Moreover, the semiconductor device includes a metal-diffusion-shield pattern in the insulating layer and spaced apart from the first conductive structure.

Abstract translation: 提供半导体器件。 半导体器件包括衬底，衬底上的第一导电结构和第一导电结构上的第二导电结构。 半导体器件包括在第一和第二导电结构的相应侧壁上的第一和第二金属扩散阻挡层。 半导体器件包括在第一和第二金属扩散阻挡层之间的绝缘层。 此外，半导体器件在绝缘层中包括金属扩散屏蔽图案并且与第一导电结构间隔开。

公开(公告)号：US20160141249A1

公开(公告)日：2016-05-19

申请号：US14937406

申请日：2015-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Joo-Hee Jang ,  Jin-Ho Chun

IPC: H01L23/532 ,  H01L25/065

CPC classification number: H01L23/53228 ,  H01L21/76843 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L25/0657 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/08121 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive structure on the first conductive structure. The semiconductor device includes first and second metal-diffusion-blocking layers on respective sidewalls of the first and second conductive structures. The semiconductor device includes an insulating layer between the first and second metal-diffusion-blocking layers. Moreover, the semiconductor device includes a metal-diffusion-shield pattern in the insulating layer and spaced apart from the first conductive structure.

Abstract translation: 提供半导体器件。 半导体器件包括衬底，衬底上的第一导电结构和第一导电结构上的第二导电结构。 半导体器件包括在第一和第二导电结构的相应侧壁上的第一和第二金属扩散阻挡层。 半导体器件包括在第一和第二金属扩散阻挡层之间的绝缘层。 此外，半导体器件在绝缘层中包括金属扩散屏蔽图案并且与第一导电结构间隔开。

公开(公告)号：US09252141B2

公开(公告)日：2016-02-02

申请号：US14326282

申请日：2014-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-Jin Moon ,  Byung-Lyul Park ,  Jae-Hwa Park

IPC: H01L27/02 ,  H01L23/48 ,  H01L27/088

CPC classification number: H01L27/0296 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/088 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A semiconductor integrated circuit device includes a TSV (Through Silicon Via) extending through a substrate, a first well in the substrate adjacent a first surface of the substrate, a gate of an active device on the first well, a charging protection well, and a charging protection gate on the charging protection well. The charging protection well is disposed in the substrate adjacent the first surface of the substrate, is interposed between the TSV hole and the first well, and surrounds the TSV hole. The charging protection gate prevents the gate of the active device from being damaged when the TSV is formed especially when using a plasma etch process to form a TSV hole in the substrate.

Abstract translation: 半导体集成电路器件包括延伸穿过衬底的TSV（贯通硅通孔），邻近衬底第一表面的衬底中的第一阱，第一阱上的有源器件的栅极，充电保护阱和 充电保护门对充电保护良好。 充电保护孔设置在基板的与基板的第一表面相邻的基板中，插入在TSV孔和第一阱之间，并且包围TSV孔。 当TSV形成时，充电保护门防止有源器件的栅极被损坏，特别是当使用等离子体蚀刻工艺在衬底中形成TSV孔时。