公开(公告)号：US20240213213A1

公开(公告)日：2024-06-27

申请号：US18599734

申请日：2024-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Chien-Sheng Chen ,  Po-Yao Lin ,  Po-Chen Lai ,  Shu-Shen Yeh

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L23/3121 ,  H01L23/49822 ,  H01L24/96 ,  H01L25/50

Abstract: A method includes bonding a first package component over a second package component. The second package component includes a plurality of dielectric layers, and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes dispensing a stress absorber on the second package component, curing the stress absorber, and forming an encapsulant on the second package component and the stress absorber.

公开(公告)号：US11996606B2

公开(公告)日：2024-05-28

申请号：US18064594

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yao Chuang ,  Po-Hao Tsai ,  Shin-Puu Jeng

IPC: H01Q1/22 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H01Q9/04 ,  H01Q19/10 ,  H01L21/683 ,  H01L21/82 ,  H01L25/065

CPC classification number: H01Q1/2283 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01Q9/0407 ,  H01Q19/10 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/82 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/92225 ,  H01L2224/95001 ,  H01L2924/1421

Abstract: A method includes bonding an antenna substrate to a redistribution structure. The antenna substrate has a first part of a first antenna, and the redistribution structure has a second part of the first antenna. The method further includes encapsulating the antenna substrate in an encapsulant, and bonding a package component to the redistribution structure. The redistribution structure includes a third part of a second antenna, and the package component includes a fourth part of the second antenna.

公开(公告)号：US11984405B2

公开(公告)日：2024-05-14

申请号：US17813102

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/5386 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/105 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/06051 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06179 ,  H01L2224/13147 ,  H01L2224/16052 ,  H01L2224/16055 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/17135 ,  H01L2224/17136 ,  H01L2224/17179 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/16052 ,  H01L2924/00012 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated.

公开(公告)号：US20240105705A1

公开(公告)日：2024-03-28

申请号：US18525976

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Po-Yao Chuang ,  Shin-Puu Jeng ,  Meng-Wei Chou ,  Meng-Liang Lin

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L21/566 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/0401

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

公开(公告)号：US11935842B2

公开(公告)日：2024-03-19

申请号：US17401616

申请日：2021-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Clinton Chao ,  Szu-Wei Lu

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/56 ,  H01L21/78 ,  H01L23/52 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L21/0214 ,  H01L21/302 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3185 ,  H01L21/32051 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/52 ,  H01L24/05 ,  H01L24/81 ,  H01L24/85 ,  H01L24/96 ,  H01L21/02123 ,  H01L21/02274 ,  H01L21/02282 ,  H01L23/585 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48175 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2224/48465 ,  H01L2224/48091 ,  H01L2924/00 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

公开(公告)号：US20240088061A1

公开(公告)日：2024-03-14

申请号：US18517489

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chia-Hsiang Lin

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/35121

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

公开(公告)号：US20240079356A1

公开(公告)日：2024-03-07

申请号：US18151623

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Chieh-Lung Lai ,  Meng-Liang Lin ,  Chun-Yueh Yang ,  Shin-Puu Jeng

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H10B80/00

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H10B80/00 ,  H01L2223/6616 ,  H01L2223/6672 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15311

Abstract: An integrated circuit package includes an interposer, the interposer including: a first redistribution layer, a second redistribution layer over the first redistribution layer in a central region of the interposer, a dielectric layer over the first redistribution layer in a periphery of the interposer, the dielectric layer surrounding the second redistribution layer in a top-down view, a third redistribution layer over the second redistribution layer and the dielectric layer, and a first direct via extending through the dielectric layer. A conductive feature of the third redistribution layer is coupled to a conductive feature of the first redistribution layer through the first direct via.

公开(公告)号：US20230411234A1

公开(公告)日：2023-12-21

申请号：US17825748

申请日：2022-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Yu Chen Lee ,  Po-Chen Lai ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Yu-Sheng Lin ,  Chien-Hung Chen

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/3675 ,  H01L23/5385 ,  H01L2224/32245 ,  H01L24/83 ,  H01L24/32

Abstract: A device includes a package substrate, an interposer having a first side bonded to the package substrate, a first die bonded to a second side of the interposer, the second side being opposite the first side, a ring on the package substrate, wherein the ring surrounds the first die and the interposer; and a heat spreader over and coupled to the ring and the first die, wherein a first coefficient of thermal expansion of a first material of the ring and a second coefficient of thermal expansion of a second material of the heat spreader are different, and wherein in a cross-sectional view a combined structure of the heat spreader and the ring have a H-shaped profile.

公开(公告)号：US20230402339A1

公开(公告)日：2023-12-14

申请号：US17840362

申请日：2022-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Chin-Hua Wang ,  Chipta Priya Laksana ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/16 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/16 ,  H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/565

Abstract: In an embodiment, a method of forming a semiconductor device includes: attaching an integrated circuit die to an interposer; forming an encapsulant over the interposer and around the integrated circuit die, a top surface of the encapsulant and a top surface of the integrated circuit die being level; forming recesses in the encapsulant; and bonding the interposer to a package substrate, wherein after bonding the interposer to the package substrate, each of the recesses being along an outer edge of the encapsulant.

公开(公告)号：US20230395581A1

公开(公告)日：2023-12-07

申请号：US17830187

申请日：2022-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Meng-Liang Lin ,  Shin-Puu Jeng

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L25/162 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/481 ,  H01L24/73

Abstract: A package is provided in accordance with some embodiments. The package includes a substrate including a first conductive via embedded in a first substrate core; a conductive pattern disposed on the first substrate core, wherein the conductive pattern includes a first conductive pad and a second conductive pad; a second substrate core disposed on the first substrate core and the conductive pattern; and a second conductive via disposed in the second substrate core and on the second conductive pad. The package also includes an encapsulant embedded in the second substrate core and in physical contact with the first conductive pad; a first die, including die connectors, embedded in the encapsulant and disposed on the first conductive pad; a redistribution structure disposed on the second conductive via, the die connectors and the encapsulant; and a second die disposed on the redistribution structure.