公开(公告)号：US08963312B2

公开(公告)日：2015-02-24

申请号：US14339341

申请日：2014-07-23

Applicant: Xintec Inc.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC: H01L23/02 ,  H01L23/48 ,  H01L21/44 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/49 ,  G06K9/00053 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06135 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/43 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/146 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.

Abstract translation: 提供了包括具有上表面，下表面和侧壁的器件衬底的堆叠芯片封装。 器件衬底包括感测区域或器件区域，信号焊盘区域和沿着侧壁从上表面向下表面延伸的浅凹陷结构。 再分配层电连接到信号焊盘区域并延伸到浅凹陷结构中。 电线具有设置在浅凹陷结构中并电连接到再分布层的第一端，以及电连接到设置在下表面下方的第一基板和/或第二基板的第二端。 还提供了一种用于形成堆叠芯片封装的方法。

公开(公告)号：US08952501B2

公开(公告)日：2015-02-10

申请号：US13950101

申请日：2013-07-24

Applicant: Xintec Inc.

Inventor： Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC: H01L29/06 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L23/49805 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L24/95 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having an upper surface and a lower surface; a device region or sensing region defined in the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; at least two recesses extending from the upper surface towards the lower surface of the semiconductor substrate, wherein sidewalls and bottoms of the recesses together form a sidewall of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to the sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有上表面和下表面的半导体衬底; 限定在所述半导体衬底中的器件区域或感测区域; 导电焊盘，位于所述半导体衬底的上表面上; 至少两个从所述半导体衬底的上表面向下表面延伸的凹槽，其中所述凹槽的侧壁和底部一起形成所述半导体衬底的侧壁; 导电层，电连接到导电焊盘并从半导体衬底的上表面延伸到半导体衬底的侧壁; 以及位于导电层和半导体衬底之间的绝缘层。

公开(公告)号：US09865526B2

公开(公告)日：2018-01-09

申请号：US14877806

申请日：2015-10-07

Applicant: XINTEC INC.

Inventor： Yu-Lung Huang

IPC: H01L23/48 ,  H01L27/146 ,  H01L25/16 ,  H01L25/00 ,  B81B7/00 ,  B81C1/00 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  B81B7/007 ,  B81C1/00238 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L25/16 ,  H01L25/50 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/02335 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/038 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/0556 ,  H01L2224/05568 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48225 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/92147 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/181 ,  H01L2224/48145 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A chip package including a first substrate having an upper surface, a lower surface and a sidewall is provided. A sensing region or device region and a conducting pad are adjacent to the upper surface. A through-hole penetrates the first substrate. A redistribution layer extends from the lower surface into the through-hole and is electrically connected to the conducting pad. The redistribution layer further laterally extends from the lower surface to protrude from the sidewall. A method for forming the chip package is also provided.

公开(公告)号：US09711425B2

公开(公告)日：2017-07-18

申请号：US15237287

申请日：2016-08-15

Applicant: XINTEC INC.

Inventor： Shu-Ming Chang ,  Po-Chang Huang ,  Tsang-Yu Liu ,  Yu-Lung Huang ,  Chi-Chang Liao

IPC: H01L23/31 ,  G06K9/00 ,  H01L23/48

CPC classification number: H01L23/3121 ,  G06K9/00013 ,  G06K9/0002 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L2224/11

Abstract: A sensing module is provided. The sensing module includes a sensing device. The sensing device includes a first substrate having a first surface and a second surface opposite thereto. The sensing device also includes a sensing region adjacent to the first surface and a conducting pad on the first surface. The sensing device further includes a redistribution layer on the second surface and electrically connected to the conducting pad. The sensing module also includes a second substrate and a cover plate bonded to the sensing device so that the sensing device is between the second substrate and the cover plate. The conducting pad is electrically connected to the second substrate through the redistribution layer. The sensing module further includes an encapsulating layer filled between the second substrate and the cover plate to surround the sensing device.

公开(公告)号：US20130193571A1

公开(公告)日：2013-08-01

申请号：US13743524

申请日：2013-01-17

Applicant: XINTEC INC.

Inventor： Yu-Lung Huang

IPC: H01L21/56 ,  H01L23/498

CPC classification number: H01L21/56 ,  B81C1/00896 ,  H01L21/561 ,  H01L23/3157 ,  H01L23/49811 ,  H01L2924/0002 ,  Y10T29/5317 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package includes: disposing a first wafer on a substrate having at least a conductive pad; stacking a second wafer on the first wafer, wherein the second wafer has a pre-open area corresponding in position to the conductive pad of the substrate; forming a protection layer on the second wafer; embrittling the protection layer on the pre-open area of the second wafer; and removing the embrittled portion of the protection layer and portions of the second and first wafers so as to form an opening to expose the conductive pad, thereby preventing an adhesive layer from being attached to a cutting tool as in the prior art.

Abstract translation: 半导体封装的制造方法包括：在至少具有导电焊盘的基板上设置第一晶片; 在所述第一晶片上堆叠第二晶片，其中所述第二晶片具有与所述衬底的所述导电焊盘相对应的位置的预开放区域; 在所述第二晶片上形成保护层; 使保护层脆化在第二晶片的预开放区域上; 并且去除保护层的脆化部分和第二和第一晶片的部分，以形成露出导电焊盘的开口，从而防止粘合剂层像现有技术那样附着在切割工具上。

公开(公告)号：US10152180B2

公开(公告)日：2018-12-11

申请号：US15061858

申请日：2016-03-04

Applicant: XINTEC INC.

Inventor： Shu-Ming Chang ,  Yu-Lung Huang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: G06F3/044 ,  H01L21/683 ,  H01L21/768 ,  G06K9/00 ,  H01L23/48 ,  H01L23/31

Abstract: This present invention provides a chip scale sensing chip package, comprising a sensing chip having a first top surface and a first bottom surface opposite to each other, a touch plate having a second top surface and a second bottom surface opposite to each other, formed above the sensing chip, and a color layer, sandwiched between the sensing chip and the touch plate, wherein the sensing chip comprises a sensing device formed nearby the first top surface and a plurality of conductive pads formed nearby the first top surface and adjacent to the sensing device, a plurality of through silicon vias exposing their corresponding conductive pads formed on the first bottom surface, a plurality of conductive structures formed on the first bottom surface, and a re-distribution layer overlaying the first bottom surface and each through silicon via to electrically connect each conductive pad and each conductive structure.

公开(公告)号：US09947716B2

公开(公告)日：2018-04-17

申请号：US15358852

申请日：2016-11-22

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Hsiao-Lan Yeh ,  Chia-Sheng Lin ,  Yi-Ming Chang ,  Po-Han Lee ,  Hui-Hsien Wu ,  Jyun-Liang Wu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chien-Min Lin

IPC: H01L27/146 ,  H01L21/48 ,  H01L21/67 ,  H01L23/18

CPC classification number: H01L27/14698 ,  H01L21/4803 ,  H01L21/67017 ,  H01L21/67132 ,  H01L23/18 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687

Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 μm to 750 μm, and the wall surface of the dam element surrounding the sensing area is a rough surface.

公开(公告)号：US09620431B2

公开(公告)日：2017-04-11

申请号：US14619658

申请日：2015-02-11

Applicant: XINTEC INC.

Inventor： Chia-Ming Cheng ,  Tsang-Yu Liu ,  Chi-Chang Liao ,  Yu-Lung Huang

IPC: H01L29/06 ,  H01L23/31

CPC classification number: H01L23/3185 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/94 ,  H01L29/0657 ,  H01L2224/0224 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/06165 ,  H01L2224/10135 ,  H01L2224/10145 ,  H01L2224/94 ,  H01L2224/03

Abstract: A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess. A method for forming the chip package is also provided.

公开(公告)号：US09425134B2

公开(公告)日：2016-08-23

申请号：US14339323

申请日：2014-07-23

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  G06K9/00 ,  H01L25/065 ,  H01L23/525 ,  H01L23/532

CPC classification number: H01L23/49805 ,  G06K9/00006 ,  G06K9/00053 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A first end of a wire is located in the shallow recess structure and is electrically connected to the redistribution layer. A second end of the wire is used for external electrical connection. A method for forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括具有上表面，下表面和侧壁的芯片。 芯片包括感测区域或器件区域以及与上表面相邻的信号焊盘区域。 浅凹陷结构位于信号垫区域的外侧，并且沿着侧壁从上表面向下表面延伸。 浅凹部结构在第一凹部下方具有至少第一凹部和第二凹部。 再分配层电连接到信号焊盘区域并延伸到浅凹陷结构中。 电线的第一端位于浅凹陷结构中，并且电连接到再分配层。 电线的第二端用于外部电气连接。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US08741683B2

公开(公告)日：2014-06-03

申请号：US14074519

申请日：2013-11-07

Applicant: Xintec Inc.

Inventor： Yu-Lung Huang ,  Tsang-Yu Liu

IPC: H01L21/00

CPC classification number: H01L24/94 ,  H01L23/3114 ,  H01L23/3171 ,  H01L27/14618 ,  H01L27/14627 ,  H01L31/048 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H04N5/2257 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region; and an auxiliary pattern having a hollow pattern formed in the spacing layer, a material pattern located between the spacing layer and the device region, or combinations thereof.