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    MEMORY CONTROLLER-CONTROLLED REFRESH ABORT
    15.
    发明申请
    MEMORY CONTROLLER-CONTROLLED REFRESH ABORT 有权

    公开(公告)号：US20170352406A1

    公开(公告)日：2017-12-07

    申请号：US15174946

    申请日：2016-06-06

    申请人： Intel Corporation

    发明人： Bruce QUERBACH ,  Kuljit S. BAINS ,  John B. HALBERT

    IPC分类号： G11C11/406 ,  G06F3/06 ,  G11C14/00

    CPC分类号： G11C11/40618 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40622 ,  G11C14/0009

    摘要： A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of operations executed by memory devices in the case where a refresh command causes refresh of multiple rows of memory. The memory controller can issue a refresh command during active operation of the memory device, which is active operation refresh as opposed to self-refresh when the memory device controls refreshing. The memory controller can then issue a refresh abort during the refresh, and prior to completion of the refresh. The memory controller thus has deterministic control over both the start of refresh as well as when the memory device can be made available for access.

    Semiconductor memory device capable of performing read operation and write operation simultaneously
    17.
    发明授权
    Semiconductor memory device capable of performing read operation and write operation simultaneously 有权

    公开(公告)号：US09633712B1

    公开(公告)日：2017-04-25

    申请号：US15131034

    申请日：2016-04-18

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Chung-Hao Cheng

    IPC分类号： G11C14/00 ,  G11C11/4063

    CPC分类号： G11C7/12 ,  G11C5/06 ,  G11C11/409 ,  G11C14/0009 ,  G11C14/0018

    摘要： A semiconductor memory device includes a charge storage element, a read transistor, and a write transistor. The charge storage element is for preserving a first data voltage. The read transistor has a first terminal coupled to the charge storage element, a second terminal coupled to a read bit line, and a control terminal coupled to a read word line. The write transistor has a first terminal coupled to the first terminal of the read transistor, a second terminal coupled to a write bit line, and a control terminal coupled to a write word line. The semiconductor memory device is able to perform a read operation and a write operation to the charge storage element simultaneously through the read transistor and the write transistor.

    Storage device and data processing method
    20.
    发明授权
    Storage device and data processing method 有权
    存储设备和数据处理方法

    公开(公告)号：US09569128B2

    公开(公告)日：2017-02-14

    申请号：US14552316

    申请日：2014-11-24

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Taro Iketaki

    IPC分类号： G06F12/00 ,  G06F3/06

    CPC分类号： G06F3/0616 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0685 ,  G11C14/0009 ,  G11C14/0054 ,  Y02D10/154

    摘要： A storage device includes a nonvolatile memory unit, a volatile memory unit, a power supply control unit configured to control power supply to the nonvolatile memory unit and the volatile memory unit, and a control unit configured to control the power supply unit to cut off the power supply to the nonvolatile memory unit and the volatile memory unit during a first operation, and control the power supply unit to cut off the power supply to the nonvolatile memory unit and to maintain the power supply to the volatile memory unit during a second operation that is different from the first operation.

    摘要翻译： 存储装置包括：非易失性存储单元，易失性存储单元，配置成控制对非易失性存储单元和易失性存储单元的电力供应的电源控制单元;以及控制单元，被配置为控制电源单元切断 在第一操作期间向非易失性存储器单元和易失性存储器单元供电，并且控制电源单元切断对非易失性存储器单元的电源，并且在第二操作期间维持对易失性存储器单元的电力供应 与第一次操作不同。