公开(公告)号：US20190229066A1

公开(公告)日：2019-07-25

申请号：US16154739

申请日：2018-10-09

Applicant: HannStar Display Corporation

Inventor： Chung-Lin CHANG ,  Hsuan-Chen LIU

IPC: H01L23/544 ,  H01L27/12

CPC classification number: H01L23/544 ,  H01L27/1218 ,  H01L27/124 ,  H01L2223/5442 ,  H01L2223/54426

Abstract: In a display panel, multiple first alignment patterns are disposed in a non-display area on a first substrate, and each first alignment pattern includes a first portion and a second portion connected to each other. Multiple second alignment patterns are disposed in the non-display area on a second substrate, and each of the second alignment patterns includes a third portion and a fourth portion. There is a first length difference between the length of each first portion along a first direction and the length of the corresponding third portion along the first direction, and the first length differences are different from each other. There is a second length difference between the length of each second portion along a second direction and the length of the corresponding fourth portion along the second direction, and the second length differences are different from each other.

公开(公告)号：US20180277456A1

公开(公告)日：2018-09-27

申请号：US15984988

申请日：2018-05-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki ABE ,  Chuichi MIYAZAKI ,  Hideo MUTOU ,  Tomoko HIGASHINO

IPC: H01L21/66 ,  B23K26/00 ,  B23K26/53 ,  H01L21/268 ,  H01L21/304 ,  H01L21/48 ,  H01L21/56 ,  H01L21/67 ,  H01L21/683 ,  H01L21/78 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L24/06 ,  B23K26/0006 ,  B23K26/40 ,  B23K26/53 ,  B23K2101/40 ,  B23K2103/50 ,  B23K2103/56 ,  G01R31/2601 ,  H01L21/268 ,  H01L21/304 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/67092 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/6838 ,  H01L21/78 ,  H01L22/12 ,  H01L22/32 ,  H01L22/34 ,  H01L23/544 ,  H01L23/562 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L25/065 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2223/5448 ,  H01L2224/02235 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06515 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.

公开(公告)号：US20180247872A1

公开(公告)日：2018-08-30

申请号：US15968312

申请日：2018-05-01

Applicant: Infineon Technologies AG

Inventor： Markus Brunnbauer ,  Franco Mariani

IPC: H01L21/78 ,  H01L21/306 ,  H01L21/308 ,  H01L21/683 ,  H01L23/544 ,  H01L21/304

CPC classification number: H01L21/78 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/544 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/5442

Abstract: Separation grooves are etched from a main surface into a semiconductor substrate. The separation grooves separate chip regions in horizontal directions parallel to the main surface. At least some of the separation grooves are spaced from a lateral outer surface of the semiconductor substrate by at most a first distance. An indentation is formed along a lateral surface. The indentation extends from the main surface into the semiconductor substrate. A minimum horizontal indentation width of the indentation is equal to or greater than the first distance. A with respect to the main surface vertical extension of the indentation is equal to or greater than a vertical extension of the separation grooves.

公开(公告)号：US10056336B2

公开(公告)日：2018-08-21

申请号：US15709733

申请日：2017-09-20

Applicant: Renesas Electronics Corporation

Inventor： Masami Koketsu ,  Toshiaki Sawada

IPC: H01L23/544 ,  H01L23/58 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L27/12 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L23/544 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/585 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2224/8113 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01054 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/1433 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00

Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.

公开(公告)号：US10043760B2

公开(公告)日：2018-08-07

申请号：US15794637

申请日：2017-10-26

Applicant: International Business Machines Corporation

Inventor： David J. Conklin ,  Allen H. Gabor ,  Sivananda K. Kanakasabapathy ,  Byeong Y. Kim ,  Fee Li Lie ,  Stuart A. Sieg

IPC: H01L21/311 ,  H01L23/544 ,  H01L21/308 ,  G03F9/00 ,  G03F7/20 ,  H01L21/033

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  G03F9/708 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected of the plurality of mandrels and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern of the sub-lithographic structure and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.

公开(公告)号：US20180144999A1

公开(公告)日：2018-05-24

申请号：US15356368

申请日：2016-11-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： KUAN-LIANG LU ,  XIN-HUA HUANG ,  YEUR-LUEN TU

IPC: H01L21/66 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/544 ,  H01L21/67

CPC classification number: H01L21/67288 ,  H01L22/12 ,  H01L22/20 ,  H01L23/544 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/80013 ,  H01L2224/80052 ,  H01L2224/8013 ,  H01L2224/80894 ,  H01L2225/06524 ,  H01L2225/06593

Abstract: A method of semiconductor wafer bonding and system thereof are proposed. A first alignment mark of a first semiconductor wafer is aligned with a second alignment mark of a second semiconductor wafer. A partial attachment is performed between the first semiconductor wafer and the second semiconductor wafer. A scanning is performed along a direction substantially parallel to a surface of the first semiconductor wafer. It is determined if a bonding defect of the partially attached first semiconductor wafer and the second semiconductor wafer exists.

公开(公告)号：US20180138132A1

公开(公告)日：2018-05-17

申请号：US15735858

申请日：2016-03-02

Applicant: Mitsubishi Electric Corporation

Inventor： Koichiro NISHIZAWA ,  Takayuki HISAKA

IPC: H01L23/00 ,  H01L23/04 ,  H01L23/48 ,  H01L23/10 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L21/4817 ,  H01L21/76898 ,  H01L23/02 ,  H01L23/04 ,  H01L23/041 ,  H01L23/10 ,  H01L23/12 ,  H01L23/14 ,  H01L23/481 ,  H01L23/544 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2924/13051 ,  H01L2924/13064 ,  H01L2924/3025 ,  H01L2924/35121 ,  H01L2224/81

Abstract: Airtightness of a hollow portion is maintained, and yield and durability are improved. A semiconductor device 1 includes a device substrate 2, a semiconductor circuit 3, a sealing frame 7, a cap substrate 8, via portions 10, electrodes 11, 12 and 13, and a bump portion 14 or the like. A hollow portion 9 in which the semiconductor circuit 3 is housed in an airtight state is provided between the device substrate 2 and the cap substrate 8. The bump portion 14 connects all the via portions 10 and the cap substrate 8. Thus, the via portions 10 can be reinforced using the bump portion 14A.

公开(公告)号：US20180122839A1

公开(公告)日：2018-05-03

申请号：US15567518

申请日：2015-04-20

Applicant: Sakai Display Products Corporation

Inventor： Nobutake Nodera ,  Shigeru Ishida ,  Ryohei Takakura ,  Yoshiaki Matsushima ,  Takao Matsumoto

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L23/544

CPC classification number: H01L27/1274 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02678 ,  H01L23/544 ,  H01L27/1229 ,  H01L27/1288 ,  H01L29/66765 ,  H01L29/786 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78669 ,  H01L29/78678 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: In the present invention, a gate electrode is formed on a substrate surface, and an insulation film is formed on the substrate surface whereon the gate electrode has been formed. A first amorphous silicon layer is formed on the substrate surface whereon the insulation film has been formed. An energy beam is irradiated onto a plurality of required sites spaced from each other in the first amorphous silicon layer to transform each of the required sites into a polysilicon layer. Each of the required sites is situated on the upper side of the gate electrode and serves as a channel region between a source and a drain. This allows other sites, which are in the first amorphous silicon layer and related to the plurality of required sites, to also be irradiated by the energy beam and ablated so as to form at the other sites a cleared portion having a required shape. Thereafter, when a metal layer for the source electrode and the drain electrode is formed, the shape of the cleared portion, which is a recessed portion, is followed, thereby forming a depression in the metal layer. Consequently, the depression is used as an alignment mark, and the source electrode and the drain electrode are formed at appropriate positions on the upper side of the channel region.

公开(公告)号：US09933672B2

公开(公告)日：2018-04-03

申请号：US14906095

申请日：2015-06-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Weihua Jia ,  Peng Jiang ,  Haipeng Yang ,  Jaikwang Kim ,  Yong Jun Yoon

IPC: G02F1/1345 ,  G02F1/1333 ,  G02F1/1339 ,  G02F1/1362 ,  G02F1/133 ,  G02F1/136 ,  G02F1/1368 ,  H01L23/544 ,  H01L23/60 ,  H01L27/02 ,  H01L27/12

CPC classification number: G02F1/136204 ,  G02F1/133 ,  G02F1/1345 ,  G02F1/136 ,  G02F1/136209 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2202/16 ,  G02F2202/28 ,  H01L23/544 ,  H01L23/60 ,  H01L27/0292 ,  H01L27/0296 ,  H01L27/124 ,  H01L27/1259 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486

Abstract: A display panel and manufacturing method thereof, and a display device are disclosed. The display panel includes an array substrate and a counter substrate. The array substrate includes a main region and a peripheral region, the main region coincides with an orthographical projection of the counter substrate on the array substrate, and at least one glue dispensing zone is arranged in the peripheral region or the main region. Conductive adhesive is provided in the glue dispensing zone, and is electrically connected to a grounded unit; an electrostatic conducting structure is provided on the counter substrate, and the conductive adhesive is electrically connected to the electrostatic conducting structure.

公开(公告)号：US09922936B1

公开(公告)日：2018-03-20

申请号：US15250991

申请日：2016-08-30

Applicant: Infineon Technologies Austria AG

Inventor： Simone Lavanga ,  Uttiya Chowdhury ,  Mattia Capriotti

IPC: H01L23/544 ,  H01L21/02 ,  H01L21/78 ,  H01L21/306 ,  H01L29/20

CPC classification number: H01L23/544 ,  H01L21/0206 ,  H01L21/02118 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02318 ,  H01L21/02387 ,  H01L21/0243 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02658 ,  H01L21/30621 ,  H01L21/78 ,  H01L29/20 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A type III-V semiconductor substrate is provided. Semiconductor material is removed from the type III-V semiconductor substrate such that the type III-V semiconductor substrate comprises one or more alignment features extending away from a main lateral surface. Each of the alignment features includes a first lateral surface that is vertically offset from the main lateral surface, and first and second vertical sidewalls that extend between the first lateral surface and the main lateral surface. An epitaxy blocker is formed on the first and second vertical sidewalls of each alignment feature. A type III-V semiconductor regrown layer is epitaxially grown on a portion of the semiconductor wafer that includes the one or more alignment features. The epitaxy blocker prevents the type III-V semiconductor regrown layer from forming on the first and second vertical sidewalls of the one or more alignment features.