公开(公告)号：US20120181071A1

公开(公告)日：2012-07-19

申请号：US13431609

申请日：2012-03-27

Applicant: Virendra R. JADHAV ,  Krystyna W. SEMKOW ,  Kamalesh K. SRIVASTAVA ,  Brian R. SUNDLOF

Inventor： Virendra R. JADHAV ,  Krystyna W. SEMKOW ,  Kamalesh K. SRIVASTAVA ,  Brian R. SUNDLOF

IPC: H05K1/09

CPC classification number: H01L24/13 ,  H01L23/562 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/13655 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13684 ,  H01L2224/16235 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/384 ,  Y10T156/10 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: A multi-layer pillar is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions

Abstract translation: 提供多层支柱。 多层柱用作芯片和基板之间的互连。 支柱具有至少一个低强度，高延展性变形区域，其被配置为吸收在芯片组装和热偏移期间施加的力

公开(公告)号：US08197612B2

公开(公告)日：2012-06-12

申请号：US12111524

申请日：2008-04-29

Applicant: James A Busby ,  Minhua Lu ,  Valerie A Oberson ,  Eric D Perfecto ,  Kamalesh K Srivastava ,  Brian R Sundlof ,  Julien Sylvestre ,  Renee L Weisman

Inventor： James A Busby ,  Minhua Lu ,  Valerie A Oberson ,  Eric D Perfecto ,  Kamalesh K Srivastava ,  Brian R Sundlof ,  Julien Sylvestre ,  Renee L Weisman

IPC: B23K35/22

CPC classification number: B23K35/262 ,  B23K2101/36

Abstract: Semiconductor packaging techniques are provided which optimize metallurgical properties of a joint using dissimilar solders. A solder composition for Controlled Collapse Chip Connection processing includes a combination of a tin based lead free solder component designed for a chip and a second solder component designed for a laminate. The total concentration of module Ag after reflow is less than 1.9% by weight. A method of manufacturing a solder component is also provided.

Abstract translation: 提供半导体封装技术，其使用不同的焊料优化接头的冶金性能。 用于受控塌陷芯片连接处理的焊料组合物包括为芯片设计的锡基无铅焊料组分和为层压板设计的第二焊料组分的组合。 回流后模块Ag的总浓度小于1.9重量％。 还提供了制造焊料组分的方法。

公开(公告)号：US07784669B2

公开(公告)日：2010-08-31

申请号：US12536122

申请日：2009-08-05

Applicant: Gareth G. Hougham ,  Kamalesh K. Srivastava ,  Sung K. Kang ,  Da-Yuan Shih ,  Brian R. Sundlof ,  S. Jay Chey ,  Donald W. Henderson ,  David R. Di Milia ,  Richard P. Ferlita ,  Roy A. Carruthers

Inventor： Gareth G. Hougham ,  Kamalesh K. Srivastava ,  Sung K. Kang ,  Da-Yuan Shih ,  Brian R. Sundlof ,  S. Jay Chey ,  Donald W. Henderson ,  David R. Di Milia ,  Richard P. Ferlita ,  Roy A. Carruthers

IPC: B23K35/24

CPC classification number: B23K1/19 ,  B23K35/262 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0215

Abstract: Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduce or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state. Further, the addition of a trace amount of nucleation sites within the composition facilitates control over the number, size, and orientations of primary intermetallic compounds in tin rich crystallite grains. Moreover, trace amounts of one or more solid and/or insoluble nucleating modifiers within a given volume of solder reduces the size of average crystallites within the composition.

Abstract translation: 简而言之，公开了一种新颖的材料方法，其中将一种或多种成核改性剂以微量添加到无铅富锡焊料合金中以产生具有降低或抑制的过冷温度特性的焊料组合物。 该改性剂是有助于减少与体心四方锡锡基无铅焊料相关的极端各向异性的物质。 将成核改性剂添加到焊料合金中不会实质上影响焊料组合物的熔点。 因此，具有成核组合物的焊料球冻结，而阵列内的其它焊球保持在熔体中。 这有效地使一个基板通过一个或多个预定的焊球被固定到另一个基板，以固定封装，而剩余的焊点处于液态。 此外，在组合物中添加微量的成核位点有助于控制富锡微晶颗粒中初级金属间化合物的数量，尺寸和取向。 此外，在给定体积的焊料中痕量的一种或多种固态和/或不溶性成核改性剂减少了组合物内平均微晶的尺寸。

公开(公告)号：US20100200271A1

公开(公告)日：2010-08-12

申请号：US12704592

申请日：2010-02-12

Applicant: Charles L. Arvin ,  Alexandre Blander ,  Peter J. Brofman ,  Donald W. Henderson ,  Gareth G. Hougham ,  Hsichang Liu ,  Eric D. Perfecto ,  Srinivasa S.N. Reddy ,  Krystyna W. Semkow ,  Kamalesh K. Srivastava ,  Brian R. Sundlof ,  Julien Sylvestre ,  Renee L. Weisman

Inventor： Charles L. Arvin ,  Alexandre Blander ,  Peter J. Brofman ,  Donald W. Henderson ,  Gareth G. Hougham ,  Hsichang Liu ,  Eric D. Perfecto ,  Srinivasa S.N. Reddy ,  Krystyna W. Semkow ,  Kamalesh K. Srivastava ,  Brian R. Sundlof ,  Julien Sylvestre ,  Renee L. Weisman

IPC: H01B5/00 ,  H01R43/00

CPC classification number: H01B1/02 ,  B23K35/0244 ,  B23K35/262 ,  B23K35/36 ,  B23K35/3602 ,  B82Y30/00 ,  C22C13/00 ,  H01B13/00 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0209 ,  H05K2201/0257 ,  Y10T29/49117 ,  H01L2924/00

Abstract: In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.

Abstract translation: 在本发明的一个实施方案中，将尺寸为1nm至1000nm的惰性纳米尺寸颗粒加入到焊球中。 惰性纳米尺寸颗粒可以包括金属氧化物，金属氮化物，金属碳化物，金属硼化物等。惰性纳米尺寸颗粒可以是单一化合物，或者可以是具有不同材料的涂层的金属材料。 在本发明的另一个实施方案中，将少量与锡形成稳定的高熔点金属间化合物的元素金属添加到焊料球中。 添加的至少一种元素金属与锡形成金属间化合物的沉淀物，其作为细颗粒分散在焊料中。

公开(公告)号：US07708909B2

公开(公告)日：2010-05-04

申请号：US12039309

申请日：2008-02-28

Applicant: Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

Inventor： Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

IPC: H01B1/04

CPC classification number: H01L23/3733 ,  B82Y30/00 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/40 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  Y10S977/788 ,  Y10T156/10 ,  Y10T428/24994 ,  H01L2224/0401

Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.

Abstract translation: 本发明一般涉及用于集成电路的导热膏，特别是但不限于石墨的自取向微孔板。

公开(公告)号：US07611923B2

公开(公告)日：2009-11-03

申请号：US11740962

申请日：2007-04-27

Applicant: Benjamin V. Fasano ,  Brian R. Sundlof

Inventor： Benjamin V. Fasano ,  Brian R. Sundlof

IPC: H01L21/44

CPC classification number: H01L25/0657 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/16152 ,  H01L2924/1627 ,  H01L2924/3025 ,  H01L2224/0401

Abstract: A stacked semiconductor apparatus has at least one die attached to a first side of a carrier substrate. A first circuitized substrate is attached to the first side of the carrier substrate and overlying the at least one die in a manner such that the first circuitized substrate serves as an electrical interconnection device and a heat spreading lid. The first circuitized substrate is further configured so as to facilitate cooling of the at least one die by at least a cross flow of a cooling medium therethrough.

Abstract translation: 叠层半导体装置具有至少一个附着在载体基板的第一侧的管芯。 第一电路化基板被附接到载体基板的第一侧并且以使得第一电路化基板用作电互连装置和散热盖的方式覆盖至少一个管芯。 第一电路化基板被进一步构造成便于通过至少一个冷却介质的横流而使至少一个管芯冷却。

公开(公告)号：US20090266447A1

公开(公告)日：2009-10-29

申请号：US12111524

申请日：2008-04-29

Applicant: JAMES A. BUSBY ,  MINHUA LU ,  VALERIE A. OBERSON ,  ERIC D. PERFECTO ,  KAMALESH K. SRIVASTAVA ,  BRIAN R. SUNDLOF ,  JULIEN SYLVESTRE ,  RENEE L. WEISMAN

Inventor： JAMES A. BUSBY ,  MINHUA LU ,  VALERIE A. OBERSON ,  ERIC D. PERFECTO ,  KAMALESH K. SRIVASTAVA ,  BRIAN R. SUNDLOF ,  JULIEN SYLVESTRE ,  RENEE L. WEISMAN

IPC: B23K35/22

CPC classification number: B23K35/262 ,  B23K2101/36

Abstract: Semiconductor packaging techniques are provided which optimize metallurgical properties of a joint using dissimilar solders. A solder composition for Controlled Collapse Chip Connection processing includes a combination of a tin based lead free solder component designed for a chip and a second solder component designed for a laminate. The total concentration of module Ag after reflow is less than 1.9% by weight. A method of manufacturing a solder component is also provided.

Abstract translation: 提供半导体封装技术，其使用不同的焊料优化接头的冶金性能。 用于受控塌陷芯片连接处理的焊料组合物包括为芯片设计的锡基无铅焊料组分和为层压板设计的第二焊料组分的组合。 回流后模块Ag的总浓度小于1.9重量％。 还提供了制造焊料组分的方法。

公开(公告)号：US07202154B2

公开(公告)日：2007-04-10

申请号：US10707693

申请日：2004-01-05

Applicant: Jon A. Casey ,  Brian R. Sundlof

Inventor： Jon A. Casey ,  Brian R. Sundlof

IPC: H01L21/4763

CPC classification number: H05K3/4061 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/092 ,  H05K2201/068 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A metallization process and material system for metallizing either blind or through vias in silicon, involving forming a low coefficient of thermal expansion composite or suspension, relative to pure metals, such as copper, silver, or gold, and filling the via holes in the silicon with the paste or suspension. The suspensions sinter with minimal bulk shrinkage, forming highly conductive structures without the formation of macroscopic voids. The selected suspension maintains a coefficient of thermal expansion closer to that of silicon.

公开(公告)号：US06916670B2

公开(公告)日：2005-07-12

申请号：US10358431

申请日：2003-02-04

Applicant: Jon A. Casey ,  James G. Balz ,  Michael Berger ,  Jerome Cohen ,  Charles Hendricks ,  Richard Indyk ,  Mark LaPlante ,  David C. Long ,  Lori A. Maiorino ,  Arthur G. Merryman ,  Glenn A. Pomerantz ,  Robert A. Rita ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Brian R. Sundlof ,  Richard P. Surprenant ,  Donald R. Wall ,  Thomas A. Wassick ,  Kathleen M. Wiley

Inventor： Jon A. Casey ,  James G. Balz ,  Michael Berger ,  Jerome Cohen ,  Charles Hendricks ,  Richard Indyk ,  Mark LaPlante ,  David C. Long ,  Lori A. Maiorino ,  Arthur G. Merryman ,  Glenn A. Pomerantz ,  Robert A. Rita ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Brian R. Sundlof ,  Richard P. Surprenant ,  Donald R. Wall ,  Thomas A. Wassick ,  Kathleen M. Wiley

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/12 ,  H01L23/498 ,  H05K1/03 ,  H05K3/00 ,  H05K3/22 ,  H01L21/00

CPC classification number: H05K3/225 ,  H01L21/4846 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K3/0029 ,  H05K3/4629 ,  H05K2203/173 ,  Y10T29/49124 ,  Y10T29/49135 ,  H01L2924/00

Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.

Abstract translation: 一种多层陶瓷修复工艺，提供了一种新的电气修复路径，以连接顶部表面通孔。 修复路径是建立在有缺陷的网和包含在多层陶瓷基片内的冗余修复网之间。 有缺陷的网和修复网各自终止在基板的表面通孔处。 使用激光器在基板上和基板上形成点火电路。 之后是有缺陷的网络与电气修复结构的电气隔离和电气修复线路的钝化。

公开(公告)号：US06823585B2

公开(公告)日：2004-11-30

申请号：US10249305

申请日：2003-03-28

Applicant: Mark J. LaPlante ,  Jon A. Casey ,  Thomas A. Wassick ,  David C. Long ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Robert A. Rita ,  Richard F. Indyk ,  Kathleen M. Wiley ,  Brian R. Sundlof ,  James Balz ,  Lori A. Maiorino ,  Donald R. Wall ,  Glenn A. Pomerantz

Inventor： Mark J. LaPlante ,  Jon A. Casey ,  Thomas A. Wassick ,  David C. Long ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Robert A. Rita ,  Richard F. Indyk ,  Kathleen M. Wiley ,  Brian R. Sundlof ,  James Balz ,  Lori A. Maiorino ,  Donald R. Wall ,  Glenn A. Pomerantz

IPC: H01R4300

CPC classification number: H05K3/242 ,  H05K1/0306 ,  H05K3/0035 ,  H05K3/048 ,  H05K3/184 ,  H05K3/225 ,  H05K2203/0191 ,  H05K2203/0264 ,  H05K2203/0574 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/49721 ,  Y10T29/49732 ,  Y10T29/49737 ,  Y10T29/49746

Abstract: A method and structure to form surface plating metallization on a substrate. Two layers of tape are applied to the surface of the substrate. A first path is cut through both layers of tape exposing the substrate surface. The first path connects at least one conductive via on the top surface of the substrate. A second path is cut through the second layer of tape exposing the first layer of tape. The second path is routed from the first path to an edge of the substrate A seed layer is deposited over the surface of the second layer of tape thereby creating a seeded plating path in the first path and a sacrificial seeded conduction path in the second path. Connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate creates a plated path on the surface of the substrate. The sacrificial path is removed when the tape is removed.

Abstract translation: 在基板上形成表面电镀金属化的方法和结构。 将两层胶带施加到基材的表面。 通过暴露衬底表面的两层带切割第一路径。 第一路径在衬底的顶表面上连接至少一个导电通孔。 通过暴露第一层胶带的第二层胶带切割第二条路径。 第二路径从第一路径路由到衬底的边缘。种子层沉积在第二层带的表面上，从而在第一路径中形成种子电镀路径，并在第二路径中形成牺牲种子传导路径。 将牺牲种子传导路径连接到衬底边缘处的电镀电位在衬底的表面上产生电镀路径。 去除胶带时，去除牺牲路径。