公开(公告)号：US20100200271A1

公开(公告)日：2010-08-12

申请号：US12704592

申请日：2010-02-12

Applicant: Charles L. Arvin ,  Alexandre Blander ,  Peter J. Brofman ,  Donald W. Henderson ,  Gareth G. Hougham ,  Hsichang Liu ,  Eric D. Perfecto ,  Srinivasa S.N. Reddy ,  Krystyna W. Semkow ,  Kamalesh K. Srivastava ,  Brian R. Sundlof ,  Julien Sylvestre ,  Renee L. Weisman

Inventor： Charles L. Arvin ,  Alexandre Blander ,  Peter J. Brofman ,  Donald W. Henderson ,  Gareth G. Hougham ,  Hsichang Liu ,  Eric D. Perfecto ,  Srinivasa S.N. Reddy ,  Krystyna W. Semkow ,  Kamalesh K. Srivastava ,  Brian R. Sundlof ,  Julien Sylvestre ,  Renee L. Weisman

IPC: H01B5/00 ,  H01R43/00

CPC classification number: H01B1/02 ,  B23K35/0244 ,  B23K35/262 ,  B23K35/36 ,  B23K35/3602 ,  B82Y30/00 ,  C22C13/00 ,  H01B13/00 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0209 ,  H05K2201/0257 ,  Y10T29/49117 ,  H01L2924/00

Abstract: In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.

Abstract translation: 在本发明的一个实施方案中，将尺寸为1nm至1000nm的惰性纳米尺寸颗粒加入到焊球中。 惰性纳米尺寸颗粒可以包括金属氧化物，金属氮化物，金属碳化物，金属硼化物等。惰性纳米尺寸颗粒可以是单一化合物，或者可以是具有不同材料的涂层的金属材料。 在本发明的另一个实施方案中，将少量与锡形成稳定的高熔点金属间化合物的元素金属添加到焊料球中。 添加的至少一种元素金属与锡形成金属间化合物的沉淀物，其作为细颗粒分散在焊料中。

公开(公告)号：US07708909B2

公开(公告)日：2010-05-04

申请号：US12039309

申请日：2008-02-28

Applicant: Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

Inventor： Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

IPC: H01B1/04

CPC classification number: H01L23/3733 ,  B82Y30/00 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/40 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  Y10S977/788 ,  Y10T156/10 ,  Y10T428/24994 ,  H01L2224/0401

Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.

Abstract translation: 本发明一般涉及用于集成电路的导热膏，特别是但不限于石墨的自取向微孔板。

公开(公告)号：US07202154B2

公开(公告)日：2007-04-10

申请号：US10707693

申请日：2004-01-05

Applicant: Jon A. Casey ,  Brian R. Sundlof

Inventor： Jon A. Casey ,  Brian R. Sundlof

IPC: H01L21/4763

CPC classification number: H05K3/4061 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/092 ,  H05K2201/068 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A metallization process and material system for metallizing either blind or through vias in silicon, involving forming a low coefficient of thermal expansion composite or suspension, relative to pure metals, such as copper, silver, or gold, and filling the via holes in the silicon with the paste or suspension. The suspensions sinter with minimal bulk shrinkage, forming highly conductive structures without the formation of macroscopic voids. The selected suspension maintains a coefficient of thermal expansion closer to that of silicon.

公开(公告)号：US06916670B2

公开(公告)日：2005-07-12

申请号：US10358431

申请日：2003-02-04

Applicant: Jon A. Casey ,  James G. Balz ,  Michael Berger ,  Jerome Cohen ,  Charles Hendricks ,  Richard Indyk ,  Mark LaPlante ,  David C. Long ,  Lori A. Maiorino ,  Arthur G. Merryman ,  Glenn A. Pomerantz ,  Robert A. Rita ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Brian R. Sundlof ,  Richard P. Surprenant ,  Donald R. Wall ,  Thomas A. Wassick ,  Kathleen M. Wiley

Inventor： Jon A. Casey ,  James G. Balz ,  Michael Berger ,  Jerome Cohen ,  Charles Hendricks ,  Richard Indyk ,  Mark LaPlante ,  David C. Long ,  Lori A. Maiorino ,  Arthur G. Merryman ,  Glenn A. Pomerantz ,  Robert A. Rita ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Brian R. Sundlof ,  Richard P. Surprenant ,  Donald R. Wall ,  Thomas A. Wassick ,  Kathleen M. Wiley

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/12 ,  H01L23/498 ,  H05K1/03 ,  H05K3/00 ,  H05K3/22 ,  H01L21/00

CPC classification number: H05K3/225 ,  H01L21/4846 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K3/0029 ,  H05K3/4629 ,  H05K2203/173 ,  Y10T29/49124 ,  Y10T29/49135 ,  H01L2924/00

Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.

Abstract translation: 一种多层陶瓷修复工艺，提供了一种新的电气修复路径，以连接顶部表面通孔。 修复路径是建立在有缺陷的网和包含在多层陶瓷基片内的冗余修复网之间。 有缺陷的网和修复网各自终止在基板的表面通孔处。 使用激光器在基板上和基板上形成点火电路。 之后是有缺陷的网络与电气修复结构的电气隔离和电气修复线路的钝化。

公开(公告)号：US06823585B2

公开(公告)日：2004-11-30

申请号：US10249305

申请日：2003-03-28

Applicant: Mark J. LaPlante ,  Jon A. Casey ,  Thomas A. Wassick ,  David C. Long ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Robert A. Rita ,  Richard F. Indyk ,  Kathleen M. Wiley ,  Brian R. Sundlof ,  James Balz ,  Lori A. Maiorino ,  Donald R. Wall ,  Glenn A. Pomerantz

Inventor： Mark J. LaPlante ,  Jon A. Casey ,  Thomas A. Wassick ,  David C. Long ,  Krystyna W. Semkow ,  Patrick E. Spencer ,  Robert A. Rita ,  Richard F. Indyk ,  Kathleen M. Wiley ,  Brian R. Sundlof ,  James Balz ,  Lori A. Maiorino ,  Donald R. Wall ,  Glenn A. Pomerantz

IPC: H01R4300

CPC classification number: H05K3/242 ,  H05K1/0306 ,  H05K3/0035 ,  H05K3/048 ,  H05K3/184 ,  H05K3/225 ,  H05K2203/0191 ,  H05K2203/0264 ,  H05K2203/0574 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/49721 ,  Y10T29/49732 ,  Y10T29/49737 ,  Y10T29/49746

Abstract: A method and structure to form surface plating metallization on a substrate. Two layers of tape are applied to the surface of the substrate. A first path is cut through both layers of tape exposing the substrate surface. The first path connects at least one conductive via on the top surface of the substrate. A second path is cut through the second layer of tape exposing the first layer of tape. The second path is routed from the first path to an edge of the substrate A seed layer is deposited over the surface of the second layer of tape thereby creating a seeded plating path in the first path and a sacrificial seeded conduction path in the second path. Connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate creates a plated path on the surface of the substrate. The sacrificial path is removed when the tape is removed.

Abstract translation: 在基板上形成表面电镀金属化的方法和结构。 将两层胶带施加到基材的表面。 通过暴露衬底表面的两层带切割第一路径。 第一路径在衬底的顶表面上连接至少一个导电通孔。 通过暴露第一层胶带的第二层胶带切割第二条路径。 第二路径从第一路径路由到衬底的边缘。种子层沉积在第二层带的表面上，从而在第一路径中形成种子电镀路径，并在第二路径中形成牺牲种子传导路径。 将牺牲种子传导路径连接到衬底边缘处的电镀电位在衬底的表面上产生电镀路径。 去除胶带时，去除牺牲路径。

公开(公告)号：US09472520B2

公开(公告)日：2016-10-18

申请号：US13590332

申请日：2012-08-21

Applicant: Virendra R. Jadhav ,  Krystyna W. Semkow ,  Kamalesh K. Srivastava ,  Brian R. Sundlof

Inventor： Virendra R. Jadhav ,  Krystyna W. Semkow ,  Kamalesh K. Srivastava ,  Brian R. Sundlof

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/562 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/13655 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13684 ,  H01L2224/16235 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/384 ,  Y10T156/10 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

Abstract translation: 提供了一种多层柱及其制造方法。 多层柱用作芯片和基板之间的互连。 支柱具有至少一个低强度，高延展性变形区域，其被配置为吸收在芯片组装和热偏移期间施加的力。

公开(公告)号：US20130016479A1

公开(公告)日：2013-01-17

申请号：US13553887

申请日：2012-07-20

Applicant: Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

Inventor： Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

IPC: C09K5/00 ,  B32B37/26 ,  H05K7/20

CPC classification number: H01L23/3733 ,  B82Y30/00 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/40 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  Y10S977/788 ,  Y10T156/10 ,  Y10T428/24994 ,  H01L2224/0401

Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.

Abstract translation: 本发明一般涉及用于集成电路的导热膏，特别是但不限于石墨的自取向微孔板。

公开(公告)号：US20120202343A1

公开(公告)日：2012-08-09

申请号：US13448500

申请日：2012-04-17

Applicant: Luc Bélanger ,  Srinivasa S.N. Reddy ,  Brian R. Sundlof

Inventor： Luc Bélanger ,  Srinivasa S.N. Reddy ,  Brian R. Sundlof

IPC: H01L21/44

CPC classification number: H01L24/13 ,  C22C19/03 ,  C23C14/025 ,  C23C14/165 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/0554 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A metallic adhesion layer is formed on a last level metal plate exposed in an opening of a passivation layer. A Ni—Cu alloy in which the weight percentage of Ni is from about 50% to about 70% is deposited by sputtering onto the metallic adhesion layer to form an underbump metallic layer. Optionally, a wetting layer comprising Cu or Au may be deposited by sputtering. A C4 ball is applied to a surface of the underbump metallic layer comprising the Ni—Cu alloy or the wetting layer for C4 processing. The sputter deposition of the Ni—Cu alloy offers economic advantages relative to known methods in the art since the Ni—Cu alloy in the composition of the present invention is non-magnetic and easy to sputter, and the consumption of the inventive Ni—Cu alloy is limited during C4 processing.

Abstract translation: 在暴露在钝化层的开口中的最后一级金属板上形成金属粘附层。 通过溅射将Ni的重量百分比为约50％至约70％的Ni-Cu合金沉积到金属粘合层上以形成下凸块金属层。 任选地，可以通过溅射沉积包含Cu或Au的润湿层。 将C4球施加到包含Ni-Cu合金或用于C4加工的润湿层的底部基底金属层的表面上。 Ni-Cu合金的溅射沉积相对于本领域已知的方法提供经济优势，因为本发明组合物中的Ni-Cu合金是非磁性的并且易于溅射，并且本发明的Ni-Cu C4加工时合金有限。

公开(公告)号：US20100207056A1

公开(公告)日：2010-08-19

申请号：US12772774

申请日：2010-05-03

Applicant: Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

Inventor： Gareth Hougham ,  Paul A. Lauro ,  Brian R. Sundlof ,  Jeffrey D. Gelorme

IPC: C09K5/00

CPC classification number: H01L23/3733 ,  B82Y30/00 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/40 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  Y10S977/788 ,  Y10T156/10 ,  Y10T428/24994 ,  H01L2224/0401

Abstract: The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.

Abstract translation: 本发明一般涉及用于集成电路的导热膏，特别是但不限于石墨的自取向微孔板。

公开(公告)号：US20090267228A1

公开(公告)日：2009-10-29

申请号：US12111510

申请日：2008-04-29

Applicant: Charles L. Arvin ,  Carla A. Bailey ,  Harry D. Cox ,  Hua Gan ,  Hsichang Liu ,  Arthur G. Merryman ,  Vall F. McClean ,  Srinivasa S. N. Reddy ,  Brian R. Sundlof

Inventor： Charles L. Arvin ,  Carla A. Bailey ,  Harry D. Cox ,  Hua Gan ,  Hsichang Liu ,  Arthur G. Merryman ,  Vall F. McClean ,  Srinivasa S. N. Reddy ,  Brian R. Sundlof

IPC: H01L23/52 ,  H01L21/44

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/03462 ,  H01L2224/03472 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05017 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05564 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: One embodiment of the present invention is directed to an under bump metallurgy material. The under bump metallurgy material of this embodiment includes an adhesion layer and a conduction layer formed on top of the adhesion layer. The under bump metallurgy material of this embodiment also includes a barrier layer plated on top of the conduction layer and a sacrificial layer plated on top of the barrier layer. The conduction layer of this embodiment includes a trench formed therein, the trench contacting a portion of the barrier layer and blocking a path of intermetallic formation between the conduction layer and the sacrificial layer.

Abstract translation: 本发明的一个实施例涉及一种凸块下金属材料。 本实施方式的凸块状冶金材料包括粘合层和形成在粘合层顶部的导电层。 该实施例的凸块下冶金材料还包括电镀在导电层顶部上的阻挡层和镀在阻挡层顶部上的牺牲层。 该实施例的导电层包括在其中形成的沟槽，沟槽接触势垒层的一部分并且阻挡导电层和牺牲层之间的金属间形成路径。