Patent search ap:("GENERAL ELECTRIC COMPANY") AND inv:"Paul Alan McConnelee" Page 3

21.

发明授权
Power overlay structure with leadframe connections 有权
Title translation: 带引线框架连接的电源覆盖结构

公开(公告)号：US09171785B2

公开(公告)日：2015-10-27

申请号：US14165725

申请日：2014-01-28

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda , Paul Alan McConnelee

IPC: H01L23/495 , H01L23/373 , H01L23/498 , H01L23/00 , H01L25/07 , H01L21/50

CPC classification number: H01L23/495 , H01L21/50 , H01L23/3735 , H01L23/49531 , H01L23/49575 , H01L23/49811 , H01L24/24 , H01L24/29 , H01L24/82 , H01L24/83 , H01L25/072 , H01L25/50 , H01L2224/04105 , H01L2224/24137 , H01L2224/24226 , H01L2224/24246 , H01L2224/29101 , H01L2224/29339 , H01L2224/32225 , H01L2224/32245 , H01L2224/48 , H01L2224/73217 , H01L2224/73267 , H01L2224/83192 , H01L2224/83424 , H01L2224/83447 , H01L2224/83801 , H01L2224/8384 , H01L2224/8385 , H01L2224/83855 , H01L2224/92144 , H01L2924/01029 , H01L2924/1203 , H01L2924/12042 , H01L2924/15747 , H01L2924/16152 , H01L2924/181 , H01L2924/19105 , H01L2924/014 , H01L2924/00014 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00015 , H01L2924/00 , H01L2924/00012

Abstract: A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.

Abstract translation: 公开了一种结合了引线框连接的功率覆盖（POL）封装结构。该POL结构包括具有电介质层的POL子模块，附着到电介质层的至少一个半导体器件，并且包括由半导体材料构成的衬底和形成在衬底上的多个连接焊盘，以及金属互连结构电耦合到所述至少一个半导体器件的多个连接焊盘，金属互连结构延伸穿过通过介电层形成的通孔，以便连接到多个连接焊盘。 POL结构还包括电耦合到POL子模块的引线框架，引线框架包括被配置为与外部电路结构互连的引线。

22.

发明申请
POWER OVERLAY STRUCTURE AND METHOD OF MAKING SAME 审中-公开
Title translation: 动力覆盖结构及其制造方法

公开(公告)号：US20140264800A1

公开(公告)日：2014-09-18

申请号：US13897685

申请日：2013-05-20

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Arun Virupaksha Gowda , Paul Alan McConnelee , Shakti Singh Chauhan

IPC: H01L23/495 , H01L23/00

CPC classification number: H01L23/49568 , H01L23/4334 , H01L23/4952 , H01L23/49541 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/83 , H01L24/92 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/24137 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/83192 , H01L2224/83801 , H01L2224/92144 , H01L2224/9222 , H01L2924/00 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/15312 , H01L2924/15747 , H01L2924/15787 , H01L2924/181

Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.

Abstract translation: 半导体器件模块包括电介质层，具有耦合到电介质层的第一表面的半导体器件和具有耦合到电介质层的第一表面的导电垫片。半导体器件还包括具有耦合到半导体器件的第二表面的第一表面和导电垫片的第二表面的导电散热器。金属化层耦合到半导体器件的第一表面和导电垫片的第一表面。金属化层延伸穿过电介质层，并通过导电垫片和散热器与半导体器件的第二表面电连接。

23.

发明申请
ULTRATHIN BURIED DIE MODULE AND METHOD OF MANUFACTURING THEREOF 有权
Title translation: 超声波模块及其制造方法

公开(公告)号：US20140183750A1

公开(公告)日：2014-07-03

申请号：US14188093

申请日：2014-02-24

Applicant: General Electric Company

Inventor： Paul Alan McConnelee , Scott Smith , Elizabeth Ann Burke

IPC: H01L21/56 , H01L23/31

CPC classification number: H01L23/5383 , H01L21/4857 , H01L21/561 , H01L23/3114 , H01L23/481 , H01L23/5226 , H01L23/5384 , H01L23/5386 , H01L23/5387 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/25 , H01L25/105 , H01L2021/60 , H01L2224/04105 , H01L2224/12105 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/92144 , H01L2224/92244 , H01L2225/1035 , H01L2225/1058 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15313 , H01L2924/3511 , H05K1/0271 , H05K1/144 , H05K1/185 , H05K1/189 , H05K3/4602 , H05K3/4644 , H05K3/4661 , H05K3/467 , H05K3/4673 , H05K2201/0187 , H05K2201/0191 , H05K2201/09136 , H05K2201/10734 , H01L2924/00

Abstract: A method of forming a buried die module includes providing an initial laminate flex layer and forming a die opening through the initial laminate flex layer. A first uncut laminate flex layer is secured to the first surface of the initial laminate flex layer by way of an adhesive material and a die is positioned within the die opening of the initial laminate flex layer and onto the adhesive material. A second uncut laminate flex layer is secured to the second surface of the initial laminate flex layer by way of an adhesive material and the adhesive materials are then cured. Vias and metal interconnects are formed in and on the first and second uncut laminate flex layers, with each of the metal interconnects extending through a respective via and being directly metalized to a metal interconnect on the initial laminate flex layer or a die pad on the die.

Abstract translation: 形成掩埋模具模块的方法包括提供初始层叠柔性层并通过初始层压柔性层形成模具开口。第一未切割层压柔性层通过粘合剂材料固定到初始层压柔性层的第一表面，并且模具定位在初始层压柔性层的模具开口内并粘附到粘合剂材料上。第二未切割层压柔性层通过粘合剂材料固定到初始层压柔性层的第二表面上，然后固化粘合剂材料。在第一和第二未切割的层叠柔性层中和第二未切割的层叠柔性层上形成通孔和金属互连，其中每个金属互连件延伸通过相应的通孔，并且直接金属化到初始层压柔性层上的金属互连或模具上的管芯焊盘。

24.

发明申请
SYSTEM AND METHOD OF CHIP PACKAGE BUILD-UP 有权
Title translation: 芯片包装的系统和方法

公开(公告)号：US20140110866A1

公开(公告)日：2014-04-24

申请号：US14138333

申请日：2013-12-23

Applicant: General Electric Company

Inventor： Paul Alan McConnelee , Kevin Matthew Durocher , Scott Smith , Laura A. Principe

IPC: H01L23/00 , H01L23/522

CPC classification number: H01L23/562 , H01L23/5226 , H01L24/19 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/97 , H01L2224/04105 , H01L2224/29101 , H01L2224/2919 , H01L2224/82039 , H01L2224/82047 , H01L2224/83101 , H01L2224/83192 , H01L2224/83194 , H01L2224/83856 , H01L2224/92 , H01L2224/92144 , H01L2224/97 , H01L2924/01005 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/0665 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15151 , H01L2924/17151 , H01L2924/19105 , H01L2224/83 , H01L2224/82 , H01L2924/00

Abstract: A system and method for chip package fabrication is disclosed. The chip package includes a base re-distribution layer having an opening formed therein, an adhesive layer having a window formed therein free of adhesive material, and a die affixed to the base re-distribution layer by way of the adhesive layer, the die being aligned with the window such that only a perimeter of the die contacts the adhesive layer. A shield element is positioned between the base re-distribution layer and adhesive layer that is generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer. The shield element is separated from the die by an air gap and is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die.

Abstract translation: 公开了一种用于芯片封装制造的系统和方法。芯片封装包括其中形成有开口的基底再分布层，具有形成在其中的没有粘合材料的窗口的粘合剂层和通过粘合剂层固定到基底再分布层的模具，模具是与窗口对齐，使得只有模具的周边接触粘合剂层。屏蔽元件位于基底再分布层和粘合剂层之间，该粘合剂层通常与形成在基底再分布层中的开口和粘合剂层的窗口对齐，使得仅屏蔽元件的周边附着到粘合剂层。屏蔽元件通过气隙与模具分离，并且被配置为可选择性地从粘合剂层移除以暴露模具的前表面。

25.

发明授权
Ultra-thin embedded semiconductor device package and method of manufacturing thereof 有权

公开(公告)号：US11605609B2

公开(公告)日：2023-03-14

申请号：US16788428

申请日：2020-02-12

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda , Paul Alan McConnelee , Shakti Singh Chauhan

IPC: H01L23/00 , H01L23/34 , H01L23/538 , H05K3/30 , H05K3/46 , H01L23/367 , H01L23/373 , H01L23/48 , H01L25/10 , H01L23/42 , H01L23/433 , H05K1/18 , H05K1/02 , H05K3/36

Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

26.

发明申请
ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME 审中-公开

公开(公告)号：US20170278782A1

公开(公告)日：2017-09-28

申请号：US15618660

申请日：2017-06-09

Applicant: General Electric Company

Inventor： Paul Alan McConnelee , Kevin Matthew Durocher , Scott Smith , Donald Paul Cunningham

IPC: H01L23/498 , H01L21/48 , H01L23/00 , H01L23/538

CPC classification number: H01L23/49838 , H01L21/4857 , H01L21/486 , H01L23/49805 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/49866 , H01L23/5389 , H01L24/19 , H01L24/82 , H01L2224/92144 , H01L2924/01029 , H01L2924/12042 , H01L2924/14 , H01L2924/00

Abstract: An electrical interconnect assembly for use in an integrated circuit package includes a mounting substrate having a thickness defined between a first surface and a second surface thereof and at least one electrically conductive pad formed on the first surface of the mounting substrate. A metallization layer coats a surface of the at least one electrically conductive pad and is electrically coupled thereto. The metallization layer also coats portion of the first surface of the mounting substrate and extends through at least one via formed through the thickness of the mounting substrate.

27.

发明授权
Integrated circuit package and method of making same 有权

公开(公告)号：US09613932B2

公开(公告)日：2017-04-04

申请号：US14742773

申请日：2015-06-18

Applicant: General Electric Company

Inventor： Paul Alan McConnelee , Arun Virupaksha Gowda

IPC: H01L25/065 , H01L23/498 , H01L23/538 , H01L23/00 , H01L21/683 , H01L21/48 , H01L25/00 , H05K3/30

CPC classification number: H01L25/0655 , H01L21/4857 , H01L21/486 , H01L21/6836 , H01L23/49822 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L24/19 , H01L24/20 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/04105 , H01L2224/2101 , H01L2224/221 , H01L2224/27003 , H01L2224/27312 , H01L2224/27318 , H01L2224/2732 , H01L2224/2741 , H01L2224/27416 , H01L2224/27418 , H01L2224/27422 , H01L2224/27436 , H01L2224/2781 , H01L2224/27848 , H01L2224/2919 , H01L2224/32225 , H01L2224/83101 , H01L2224/83191 , H01L2224/83192 , H01L2224/83855 , H01L2224/83856 , H01L2224/92 , H01L2224/9202 , H01L2224/92144 , H01L2224/94 , H01L2924/07802 , H01L2924/12042 , H01L2924/3511 , H05K3/305 , H01L2224/27 , H01L2224/83 , H01L2224/19 , H01L21/78 , H01L2924/00013 , H01L2924/00014 , H01L2924/0665 , H01L2924/00

Abstract: A chip package includes a first die with an active surface having at least one die pad positioned thereon; a first adhesive layer having a first surface coupled to the active surface of the first die and a second surface opposite the first surface; and a first dielectric layer having a top surface. A first portion of the top surface of the first dielectric layer is coupled to the second surface of the first adhesive layer. A second portion of the top surface of the first dielectric layer, distinct from the first portion, is substantially free of adhesive.

28.

发明申请
ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME 有权
Title translation: 用于集成电路封装的电气互连及其制造方法

公开(公告)号：US20160211208A1

公开(公告)日：2016-07-21

申请号：US15082501

申请日：2016-03-28

Applicant: General Electric Company

Inventor： Paul Alan McConnelee , Kevin Matthew Durocher , Scott Smith , Donald Paul Cunningham

IPC: H01L23/498 , H01L23/538 , H01L21/48

CPC classification number: H01L23/49838 , H01L21/4857 , H01L21/486 , H01L23/49805 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/49866 , H01L23/5389 , H01L24/19 , H01L24/82 , H01L2224/92144 , H01L2924/01029 , H01L2924/12042 , H01L2924/14 , H01L2924/00

Abstract: An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads.

Abstract translation: 用于嵌入式芯片封装的互连组件包括介电层，包括上接触焊盘的第一金属层，包括下接触焊盘的第二金属层和通过介电层形成并与上接触焊盘和下接触焊盘接触的金属化连接，以形成电它们之间的连接。上接触焊盘的第一表面固定到电介质层的顶表面，并且下接触焊盘的第一表面固定到电介质层的底表面。互连组件的第一侧的输入/输出（I / O）形成在下接触焊盘的与下接触焊盘的第一表面相对的表面上，并且第二侧的I / O 互连组件形成在与上接触焊盘的第一表面相对的上接触焊盘的表面上。