公开(公告)号：US20210217640A1

公开(公告)日：2021-07-15

申请号：US17219351

申请日：2021-03-31

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Gerald Lackner ,  Walter Horst Leitgeb ,  Michael Lecher

IPC: H01L21/67 ,  G01B11/27 ,  H01L21/78 ,  H01L21/66 ,  H01L21/68

Abstract: In an embodiment an apparatus includes a receptacle configured to receive a wafer, a light port configured to emit light from a source of light so as to shine the light on an edge of the wafer, wherein the light port is an opening located on a surface of the receptacle and a light sensitive element configured to receive light that passed the edge of the wafer and to form a detection signal based on the received light, wherein the light port is located underneath the wafer.

公开(公告)号：US10388610B2

公开(公告)日：2019-08-20

申请号：US15417618

申请日：2017-01-27

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer

IPC: G01N21/64 ,  H01L23/544 ,  G01N21/95 ,  G01N21/956 ,  H01L21/66 ,  H01L21/683

Abstract: An apparatus for inspecting a plurality of electronic chips singularized from a wafer, wherein the apparatus comprises an electromagnetic radiation source arranged and configured for illuminating at least part of a first main surface of the singularized wafer with electromagnetic radiation, and a detection unit configured for detecting electromagnetic radiation from a side facing a second main surface of the singularized wafer and opposing the first main surface.

公开(公告)号：US09966277B2

公开(公告)日：2018-05-08

申请号：US15361108

申请日：2016-11-25

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andre Schmenn ,  Damian Sojka ,  Isabella Goetz ,  Gudrun Stranzl ,  Sebastian Werner ,  Thomas Fischer ,  Carsten Ahrens ,  Edward Fuergut

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/498 ,  H01L27/02 ,  H01L23/31 ,  H01L29/861

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49838 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/861 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.

公开(公告)号：US09780161B2

公开(公告)日：2017-10-03

申请号：US14837880

申请日：2015-08-27

Applicant: Infineon Technologies AG

Inventor： Markus Menath ,  Thomas Fischer ,  Hermann Wendt

IPC: H01F17/02 ,  H01F38/14 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02 ,  H01F17/00 ,  H01F41/04 ,  H01L23/528 ,  H01L27/08 ,  H01L21/768 ,  H01L21/50 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L28/10 ,  H01F17/0006 ,  H01F17/02 ,  H01F41/042 ,  H01L21/0274 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/64 ,  H01L27/08 ,  H01L2224/48095 ,  H01L2224/48137 ,  Y10T29/4902 ,  H01L2924/00014

Abstract: A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.

公开(公告)号：US20170033066A1

公开(公告)日：2017-02-02

申请号：US15295631

申请日：2016-10-17

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Ulrike Fastner ,  Alexander Heinrich ,  Thomas Fischer

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/268 ,  H01L23/31 ,  H01L21/78

CPC classification number: H01L24/05 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3086 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/94 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02205 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05005 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05554 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/10126 ,  H01L2224/11009 ,  H01L2224/11011 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11845 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/26125 ,  H01L2224/27009 ,  H01L2224/27019 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/27845 ,  H01L2224/29007 ,  H01L2224/29013 ,  H01L2224/291 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/206 ,  H01L2924/2064 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01032 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/27

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

Abstract translation: 根据本发明的实施例，形成半导体器件的方法包括在衬底的第一主表面上形成接触层。 衬底包括由切口区域分隔开的器件区域。 接触层设置在切口区域和器件区域中。 在器件区域上形成结构化的焊料层。 在形成结构化的焊料层之后，在切割区域处露出接触层。 切割区域中的接触层和基底。

公开(公告)号：US20160343662A1

公开(公告)日：2016-11-24

申请号：US15223851

申请日：2016-07-29

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Juergen Foerster ,  Werner Robl ,  Andreas Stueckjuergen

IPC: H01L23/535 ,  H01L21/306

CPC classification number: H01L23/535 ,  H01L21/30604 ,  H01L21/32134 ,  H01L21/76838 ,  H01L21/76885 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L2221/1078 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05193 ,  H01L2224/05647 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.

Abstract translation: 一个或多个实施例涉及制造半导体结构的方法，包括：提供工件; 在工件上形成阻挡层; 在阻挡层上形成分离层; 在分离层上形成导电层; 并湿式蚀刻导电层。

公开(公告)号：US09196568B2

公开(公告)日：2015-11-24

申请号：US14042750

申请日：2013-10-01

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn ,  Edward Fuergut

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a die including at least one electronic component and a first terminal on a first side of the die and a second terminal on a second side of the die opposite the first side, wherein the first side being the main processing side of the die, and the die further including at least a third terminal on the second side; a first electrically conductive structure providing current flow from the third terminal on second side of the die to the first side through the die; a second electrically conductive structure on the first side of the die laterally coupling the second terminal with the first electrically conductive structure; and an encapsulation material disposed at least over the first side of the die covering the first terminal and the second electrically conductive structure.

Abstract translation: 提供了一种安排。 该装置可以包括：模具，其包括至少一个电子部件和在模具的第一侧上的第一端子，以及在模具的与第一侧相对的第二侧上的第二端子，其中第一侧是主要处理侧 所述管芯和所述管芯还包括在所述第二侧上的至少第三端子; 第一导电结构，其提供从模具的第二侧上的第三端子到通过模具的第一侧的电流; 在所述模具的第一侧上的第二导电结构将所述第二端子与所述第一导电结构横向地联接; 以及封装材料，其至少设置在覆盖所述第一端子和所述第二导电结构的所述管芯的所述第一侧的上方。

公开(公告)号：US09093385B2

公开(公告)日：2015-07-28

申请号：US13903013

申请日：2013-05-28

Applicant: Infineon Technologies AG

Inventor： Anja Gissibl ,  Hermann Wendt ,  Thomas Fischer ,  Bernhard Weidgans ,  Gudrun Stranzl ,  Tobias Schmidt ,  Dietrich Bonart

IPC: H01L21/00 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/78

CPC classification number: H01L21/78 ,  H01L21/28568 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76841 ,  H01L21/76892

Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.

Abstract translation: 提供了一种用于处理半导体工件的方法，其可以包括：提供包括设置在半导体工件侧面的金属化层堆叠的半导体工件，金属化层堆叠包括至少第一层和设置在第一层上的第二层 层，其中所述第一层包含第一材料，并且所述第二层包含不同于所述第一材料的第二材料; 图案化金属化层堆叠，其中图案化金属化层堆叠包括通过蚀刻溶液湿法蚀刻第一层和第二层，蚀刻溶液对于第一材料和第二材料具有至少基本上相同的蚀刻速率。

公开(公告)号：US09006898B2

公开(公告)日：2015-04-14

申请号：US14060734

申请日：2013-10-23

Applicant: Infineon Technologies AG

Inventor： Roland Hampp ,  Thomas Fischer ,  Uwe Hoeckele

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L21/66

CPC classification number: H01L24/03 ,  H01L21/02068 ,  H01L21/02071 ,  H01L21/76837 ,  H01L21/76838 ,  H01L22/32 ,  H01L23/498 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03903 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/051 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/06505 ,  H01L2224/06515 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0428 ,  H01L2924/0518 ,  H01L2924/0529 ,  H01L2924/14 ,  H01L2924/01015 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer.

Abstract translation: 公开了半导体器件和方法。 半导体器件包括具有第一区域和第二区域的衬底以及布置在衬底上的绝缘层。 第一导电层布置在第一区域中的绝缘层中或绝缘层中，并且第二导电层布置在第二区域中的绝缘层中或其上。 第一导电层包括第一导电材料，第二导电层包括第二导电材料，其中第一导电材料不同于第二导电材料。 金属层布置在第一导电层上。

公开(公告)号：US11637028B2

公开(公告)日：2023-04-25

申请号：US17219351

申请日：2021-03-31

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Gerald Lackner ,  Walter Horst Leitgeb ,  Michael Lecher

IPC: H01L21/67 ,  G01B11/27 ,  H01L21/68 ,  H01L21/78 ,  H01L21/66

Abstract: In an embodiment an apparatus includes a receptacle configured to receive a wafer, a light port configured to emit light from a source of light so as to shine the light on an edge of the wafer, wherein the light port is an opening located on a surface of the receptacle and a light sensitive element configured to receive light that passed the edge of the wafer and to form a detection signal based on the received light, wherein the light port is located underneath the wafer.