Patent search ap:("Intel Corporation") AND inv:"Rajasekaran Swaminathan" Page 3

21.

发明申请
PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGE 审中-公开

公开(公告)号：US20190206792A1

公开(公告)日：2019-07-04

申请号：US15857515

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Andrew Collins , Bharat P. Penmecha , Rajasekaran Swaminathan , Ram Viswanath

IPC: H01L23/528 , H01L23/538 , H01L25/065 , H01L25/18 , H01L23/00

CPC classification number: H01L23/5385 , H01L23/49838 , H01L23/5383

Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

22.

发明授权
Printed circuit board with a recess to accommodate discrete components in a package 有权

公开(公告)号：US10187996B2

公开(公告)日：2019-01-22

申请号：US15459787

申请日：2017-03-15

Applicant: Intel Corporation

Inventor： Rajasekaran Swaminathan , Ram S. Viswanath

IPC: H05K1/18 , H05K1/11 , H05K3/00 , H05K3/30 , H05K3/46

Abstract: Embodiments of the present disclosure provide techniques for a printed circuit board (PCB) with a recess to accommodate discrete components of a package attachable to the PCB, in accordance with some embodiments. In one embodiment, a PCB may include a recess disposed in at least a portion of the PCB, to receive at least a portion of a package. The package may be attachable to the PCB via a plurality of connectors. The connectors may be disposed on a side of the package that faces the PCB. The portion of the package may include one or more discrete components disposed on the side of the package that faces the PCB. The recess may have a depth to accommodate those discrete components that have a height that is greater than a height of the connectors. Other embodiments may be described and/or claimed.

23.

发明授权
Interconnect cable with edge finger connector 有权

公开(公告)号：US10074920B2

公开(公告)日：2018-09-11

申请号：US14822693

申请日：2015-08-10

Applicant: INTEL CORPORATION

Inventor： Donald T. Tran , Rajasekaran Swaminathan

IPC: H01R12/00 , H01R12/72 , H01R43/20 , H01R13/6581 , H01R12/71 , H01R12/81 , H01R13/6592

CPC classification number: H01R12/721 , H01R12/714 , H01R12/81 , H01R13/6581 , H01R13/6592 , H01R43/205 , Y10T29/49174 , Y10T29/49176

Abstract: Embodiments of the present disclosure are directed to an interconnect cable including a edge finger connector, and associated configurations and methods. The edge finger connector may be disposed at a first end of the interconnect cable and may connect the interconnect cable to an edge finger included in or coupled to a package substrate. The package substrate may be included in a processor package assembly, and a processor may be mounted on the substrate. The interconnect cable may include one or more elongate conductors, with contacts directly coupled to respective conductors. A second connector may be disposed at a second end of the interconnect cable, and may couple the interconnect cable to a small form-factor pluggable (SFP) case that is configured to connect the interconnect cable to an SFP cable. Other embodiments may be described and claimed.

24.

发明授权
Double-mated edge finger connector 有权
Title translation: 双重配对边缘指接头

公开(公告)号：US09502800B2

公开(公告)日：2016-11-22

申请号：US14269795

申请日：2014-05-05

Applicant: Intel Corporation

Inventor： Donald T. Tran , Srikant Nekkanty , Rajasekaran Swaminathan

IPC: H01R12/00 , H01R12/73 , H01R12/71 , H01R12/72

CPC classification number: H01R12/732 , H01R12/714 , H01R12/721

Abstract: A double-mated edge finger connector that is configured to double the connector density without resorting to a reduction in pitch. A first connector defines a first slot configured to receive and permit horizontal displacement of an edge finger of a second board relative thereto, while a second connector defines a second slot configured to receive and permit horizontal displacement of an edge finger of a first board relative thereto, to thereby establish an electrical connection between the first board and the second board.

Abstract translation: 双配合边缘指状连接器，其被配置为使连接器密度加倍，而不需要减小间距。第一连接器限定配置成接收并允许第二板相对于其的边缘指状物的水平位移的第一槽，而第二连接器限定第二槽，其构造成接收和允许第一板相对于其的边缘手指的水平位移，从而在第一板和第二板之间建立电连接。

25.

发明授权
Forming sacrificial composite materials for package-on-package architectures and structures formed thereby 有权

公开(公告)号：US09472519B2

公开(公告)日：2016-10-18

申请号：US14658089

申请日：2015-03-13

Applicant: INTEL CORPORATION

Inventor： Rajasekaran Swaminathan , Leonel R. Arana , Yoshihiro Tomita , Yosuke Kanaoka

IPC: H01L23/00 , H01L25/10 , H01L21/48 , H01L23/498 , H05K3/34

CPC classification number: H01L24/16 , H01L21/4853 , H01L23/3157 , H01L23/49816 , H01L23/49894 , H01L24/11 , H01L24/13 , H01L24/14 , H01L25/0657 , H01L25/105 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/11849 , H01L2224/16012 , H01L2224/16147 , H01L2224/16225 , H01L2225/06513 , H01L2225/06527 , H01L2225/1058 , H01L2924/00014 , H01L2924/181 , H05K3/3452 , H05K3/3484 , H05K2203/043 , H05K2203/083 , H05K2203/1476 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556

Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.

26.

发明授权
Integrated circuit connectors 有权
Title translation: 集成电路连接器

公开(公告)号：US09265170B2

公开(公告)日：2016-02-16

申请号：US14065281

申请日：2013-10-28

Applicant: INTEL CORPORATION

Inventor： Rajasekaran Swaminathan , Ram S. Viswanath , Sanka Ganesan , Gaurav Chawla , Joshua D. Heppner , Jeffory L. Smalley , Vijaykumar Krithivasan , David J. Llapitan , Neal E. Ulen , Donald T. Tran

IPC: H01R12/00 , H05K1/00 , H05K7/10 , H01R12/71 , H01R13/24

CPC classification number: H05K7/10 , H01R12/00 , H01R12/716 , H01R13/2442 , H05K1/00 , Y10T29/49169

Abstract: Embodiments related to integrated circuit (IC) connectors are described. In some embodiments, an IC assembly may include an IC package substrate, an intermediate member, and a male connector. The IC package substrate may have first signal contacts on a top or bottom surface, and the bottom surface may have second signal contacts for coupling with a socket on a circuit board. The intermediate member may have a first end coupled to the first signal contacts and a second end extending beyond the side surface. The male connector may be disposed at the second end of the intermediate member, and may have signal contacts coupled to the signal contacts of the intermediate member. The male connector may be mateable with a female connector when the female connector is brought into engagement in a direction parallel to the axis of the intermediate member. Other embodiments may be disclosed and/or claimed.

Abstract translation: 描述了与集成电路（IC）连接器相关的实施例。在一些实施例中，IC组件可以包括IC封装衬底，中间构件和阳连接器。 IC封装基板可以在顶表面或底表面上具有第一信号触点，并且底表面可以具有用于与电路板上的插座耦合的第二信号触点。中间构件可以具有联接到第一信号触头的第一端和延伸超过侧表面的第二端。阳连接器可以设置在中间构件的第二端处，并且可以具有联接到中间构件的信号触点的信号触点。当阴连接器沿平行于中间构件的轴线的方向接合时，阳连接器可与母连接器配合。可以公开和/或要求保护其他实施例。

27.

发明授权
BGA STIM package architecture for high performance systems 有权

公开(公告)号：US11817364B2

公开(公告)日：2023-11-14

申请号：US16017582

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Rajasekaran Swaminathan , Mukul Renavikar

IPC: H01L23/367 , H01L23/373 , H01L23/00

CPC classification number: H01L23/367 , H01L23/3736 , H01L24/06 , H01L24/09 , H01L24/17 , H01L2924/014 , H01L2924/0105 , H01L2924/01029 , H01L2924/01047 , H01L2924/01049 , H01L2924/01083 , H01L2924/15311

Abstract: Embodiments include semiconductor packages and methods of forming such packages. A semiconductor package includes a die on a package substrate, an integrated heat spreader (IHS) on the package substrate and above the die, and a solder thermal interface material (STIM) coupling the die to the IHS. The semiconductor package includes a low-temperature solder (LTS) paste comprising an alloy of tin and bismuth (Bi), and the LTS paste on a bottom surface of the package substrate having a ball grid array. The LTS paste may have a weight percentage of Bi greater than 35% and a melting point less than or equal to a melting point of the STIM, where the STIM includes indium. The weight percentage of Bi may be between approximately 35% to 58%. The semiconductor package may include a solder ball coupling the LTS paste on the package substrate to the LTS paste on a second package substrate.

28.

发明授权
Multiple die package using an embedded bridge connecting dies 有权

公开(公告)号：US11742293B2

公开(公告)日：2023-08-29

申请号：US16480654

申请日：2017-03-22

Applicant: Intel Corporation

Inventor： Yidnekachew S. Mekonnen , Kemel Aygun , Ravindranath V. Mahajan , Christopher S. Baldwin , Rajasekaran Swaminathan

IPC: H01L23/538 , H01L21/48 , H01L23/14 , H01L23/00 , H01L25/065 , H01L25/00

CPC classification number: H01L23/5381 , H01L21/486 , H01L21/4853 , H01L23/145 , H01L23/5383 , H01L23/5386 , H01L24/16 , H01L25/0655 , H01L25/50 , H01L2224/16227 , H01L2224/16235

Abstract: A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.

29.

发明申请
CPU PACKAGE SUBSTRATES WITH REMOVABLE MEMORY MECHANICAL INTERFACES 审中-公开

公开(公告)号：US20180007791A1

公开(公告)日：2018-01-04

申请号：US15702709

申请日：2017-09-12

Applicant: Intel Corporation

Inventor： Mani Prakash , Thomas T. Holden , Jeffory L. Smalley , Ram S. Viswanath , Bassam N. Coury , Dimitrios Ziakas , Chong J. Zhao , Jonathan W. Thibado , Gregorio R. Murtagian , Kuang C. Liu , Rajasekaran Swaminathan , Zhichao Zhang , John M. Lynch , David J. Llapitan , Sanka Ganesan , Xiang Li , George Vergis

IPC: H05K1/18 , H01L23/00 , H01L23/498 , H01R12/71 , H01R12/79

CPC classification number: H05K1/181 , H01L23/00 , H01L23/498 , H01L2224/16225 , H01L2924/15311 , H01R12/712 , H01R12/79 , H05K2201/10159 , H05K2201/10325 , Y02P70/611

Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.