中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

36 records (took 0.019 seconds)

    High density edge mounting of chips
    21.
    发明授权
    High density edge mounting of chips 失效
    高密度边缘安装芯片

    公开(公告)号：US5903437A

    公开(公告)日：1999-05-11

    申请号：US785195

    申请日：1997-01-17

    Applicant: Mark Vincent Pierson ,  Thurston Bryce Youngs, Jr.

    Inventor： Mark Vincent Pierson ,  Thurston Bryce Youngs, Jr.

    IPC: H01L21/60 ,  H01L23/367 ,  H01L23/44 ,  H01L23/473 ,  H01L23/482 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K7/20

    CPC classification number: H01L25/0657 ,  H01L23/3675 ,  H01L23/473 ,  H01L23/482 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/0002

    Abstract: An integrated circuit package derives increased mechanical robustness and electrical reliability consistent with increased heat dissipation capacity by edge bonding of integrated circuit chips onto a substrate such as a chip, board, module or another integrated circuit by forming a solder or conductive adhesive bond between a bonding/contact pad on the substrate and a metallization feature extending at least on limited opposing areas of major surfaces of the chip and, preferably, across the edge of the chip. Thermally conducting material contained in a cap may provide additional, distributed support for the chip by a combination of viscosity and density providing buoyancy of the chips. Alternatively, a cap may be provided which further stabilizes the edge-mounting of chips while increasing velocity of cooling fluid against the chips. Novel techniques of forming a metallization feature across the edge of a chip with high efficiency and manufacturing yield includes enclosure of chips or strips of chips in a tool including a grooved mask or enclosing the chips or strips of chips in a resist which may be exposed and developed using at least a portion of the same tool.

    Abstract translation: 集成电路封装通过在诸如芯片，板，模块或另一集成电路之类的衬底（例如芯片，板，模块或另一集成电路）上边缘焊接来形成增强的散热能力，从而提高了机械稳定性和电气可靠性。 /接触焊盘和金属化特征，其至少在芯片的主要表面的有限的相对区域上延伸，并且优选地跨越芯片的边缘延伸。 容纳在盖中的导热材料可以通过提供芯片浮力的粘度和密度的组合来为芯片提供附加的分布式支撑。 或者，可以提供帽，其进一步稳定了片的边缘安装，同时增加了对芯片的冷却流体的速度。 在高效率和制造成品率的跨芯片边缘形成金属化特征的新技术包括在工具中包括芯片或芯片条，其包括带槽的掩模或将芯片或条带包围在可能暴露的抗蚀剂中， 使用相同工具的至少一部分开发。

    Chip stacking by edge metallization
    22.
    发明授权
    Chip stacking by edge metallization 失效
    通过边缘金属化的芯片堆叠

    公开(公告)号：US5818107A

    公开(公告)日：1998-10-06

    申请号：US785187

    申请日：1997-01-17

    Applicant: Mark Vincent Pierson ,  Thurston Bryce Youngs, Jr.

    Inventor： Mark Vincent Pierson ,  Thurston Bryce Youngs, Jr.

    IPC: H01L21/60 ,  H01L23/50 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L23/10

    CPC classification number: H01L25/0657 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06589 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312

    Abstract: An integrated circuit package derives increased mechanical robustness and electrical reliability consistent with increased heat dissipation capacity by bonding of integrated circuit chips into a chip stack and bonding the chip stack onto a substrate such as a chip, board, module or another integrated circuit by forming a solder or conductive adhesive bond between a bonding/contact pad on the substrate and a metallization feature extending at least on limited opposing areas of major surfaces of the chip and across the edge of the chip. Thickness of the metallization feature and bonding material provides a "stand-off" between chips allowing improved heat dissipation by fluid flow, conduction through a viscous thermally conducting material and/or a heat sink disposed between chips in the stack. Novel techniques of forming a metallization feature across the edge of a chip with high efficiency and manufacturing yield includes enclosure of chips or strips of chips in a tool including a grooved mask or enclosing the chips or strips of chips in a resist which may be exposed and developed using at least a portion of the same tool. An application provides a package including heat sinking of a microprocessor master chip in combination with stack of slave chips as memory, logic macros, cross-bar switches and the like which may also include heat sinks between chips in each chip stack.

    Abstract translation: 集成电路封装通过将集成电路芯片接合到芯片堆叠中并且将芯片堆叠结合到诸如芯片，板，模块或另一集成电路的基板上，通过形成 焊料或导电粘合剂结合在衬底上的接合焊盘和至少在芯片的主要表面的有限的相对区域上延伸并穿过芯片的边缘的金属化特征。 金属化特征和接合材料的厚度在芯片之间提供“间隔”，允许通过流体流动改善散热，通过粘性导热材料的传导和/或布置在堆叠中的芯片之间的散热器。 在高效率和制造成品率的跨芯片边缘形成金属化特征的新技术包括在工具中包括芯片或芯片条，其包括带槽的掩模或将芯片或条带包围在可能暴露的抗蚀剂中， 使用相同工具的至少一部分开发。 一种应用提供了包括微处理器主芯片与作为存储器，逻辑宏，交叉开关等的堆叠的堆叠的散热器的封装，其还可以包括每个芯片堆栈中的芯片之间的散热器。

    Formable structure between two objects
    24.
    发明授权
    Formable structure between two objects 失效
    两个对象之间的形式化结构

    公开(公告)号：US07335325B1

    公开(公告)日：2008-02-26

    申请号：US10636874

    申请日：2003-08-08

    Applicant: Mark Vincent Pierson

    Inventor： Mark Vincent Pierson

    IPC: B29D31/00

    CPC classification number: B29C67/0037 ,  A63B53/14 ,  A63B60/08 ,  B29L2031/463 ,  B29L2031/507 ,  B29L2031/5227 ,  B29L2031/5245 ,  B29L2031/7252 ,  B43K23/008

    Abstract: The present invention to be personalized is fitted with a sealed chamber. The chamber is defined by an object and a thin, flexible member. When it is desired to personalize the object, the sealed chamber is filled with uncured paste having predetermined characteristics. The object to be personalized then is brought into contact with a human; thereafter, the paste cures in place to complete the personalizing process.

    Abstract translation: 要个性化的本发明装配有密封室。 室由物体和薄而柔软的构件限定。 当需要对物体进行个性化时，密封室中填充有预定特性的未固化糊料。 然后将个性化的对象与人接触; 此后，糊状物固化到位以完成个性化过程。

    Floating interposer
    25.
    发明授权
    Floating interposer 有权
    浮动插值器

    公开(公告)号：US06774315B1

    公开(公告)日：2004-08-10

    申请号：US09577457

    申请日：2000-05-24

    Applicant: Mark Vincent Pierson ,  Jennifer Rebecca Sweterlitsch ,  Charles Gerard Woychik ,  Thurston Bryce Youngs, Jr.

    Inventor： Mark Vincent Pierson ,  Jennifer Rebecca Sweterlitsch ,  Charles Gerard Woychik ,  Thurston Bryce Youngs, Jr.

    IPC: H01R1214

    CPC classification number: H01R12/52 ,  H01L23/49827 ,  H01L2924/0002 ,  H01R12/57 ,  H01R13/2414 ,  H05K3/3436 ,  H05K3/42 ,  H05K7/1061 ,  H05K13/0465 ,  H05K2201/0133 ,  H05K2201/09836 ,  H05K2201/10378 ,  Y02P70/613 ,  Y10T29/49124 ,  Y10T29/4913 ,  H01L2924/00

    Abstract: A flexible, compliant layer of a single low modulus material for connecting a chip die directly to a circuit card without encapsulation. The flexible compliant layer provides stress relief caused by CTE thermal mismatch in chip die and circuit card. An array of copper plated vias are formed in said compliant layer with each via terminating on opposing surfaces of the layer in copper pads. Rather than copper, other metals, such as gold or nickel, may also be used. An array of holes may be positioned between said array of vias to provide additional resiliency. The plated vias may be angled with respect to said opposing surfaces to allow additional vertical and horizontal stress relief. Connection of the pads on one surface to high melt C-4 solder balls or columns on a chip die results in solder filled vias. Low melt solder connection of the pads on the other surface to a circuit card allows non-destructive rework of the cards.

    Abstract translation: 用于将芯片裸片直接连接到电路卡而不封装的单个低模量材料的柔性兼容层。 灵活的柔性层提供了芯片和电路卡中CTE热失配引起的应力消除。 在所述顺应层中形成镀铜通孔的阵列，每个通孔终止于铜衬垫的相对表面上。 而不是铜，也可以使用其他金属，例如金或镍。 一组孔可以位于所述通孔阵列之间以提供额外的弹性。 电镀通孔可以相对于所述相对的表面成角度，以允许额外的垂直和水平应力释放。 将一个表面上的焊盘与芯片模具上的高熔点C-4焊球或柱的连接导致焊料填充的通孔。 将另一个表面上的焊盘的低熔点焊接连接到电路卡允许卡的非破坏性返修。

    Method for forming solder connections on a circuitized substrate
    26.
    发明授权
    Method for forming solder connections on a circuitized substrate 有权
    在电路化基板上形成焊接连接​​的方法

    公开(公告)号：US06708871B2

    公开(公告)日：2004-03-23

    申请号：US10041392

    申请日：2002-01-08

    Applicant: Mark Vincent Pierson

    Inventor： Mark Vincent Pierson

    IPC: B23K3706

    CPC classification number: B23K3/0607 ,  B23K2101/42 ,  H05K3/0035 ,  H05K3/28 ,  H05K3/3457 ,  H05K2203/0126 ,  H05K2203/0139

    Abstract: A method of forming solder connections on a circuitized substrate having connection pads is provided. A laser ablatable solder mask material, preferably an epoxy, is degassed and then dispensed as a liquid onto the substrate over the circuitization. The surface of the solder mask material as applied is leveled, and the solder mask material is then cured to form a solder mask. Openings are laser ablated in the solder mask material to reveal those connection pads which are to receive solder to form the solder connections. Liquid solder is dispensed under pressure in a confined space into the openings as blades move laterally on top of the solder mask to fill the openings in the solder mask. The solder material is then solidified to form domed solder bumps in the openings.

    Abstract translation: 提供了一种在具有连接焊盘的电路化基板上形成焊接连接​​的方法。 激光可烧蚀的焊料掩模材料（优选环氧树脂）被脱气，然后通过电路作为液体分配到衬底上。 涂覆的焊料掩模材料的表面平整，然后使焊接掩模材料固化以形成焊接掩模。 在焊料掩模材料中激光烧蚀开口，露出要接收焊料以形成焊料连接的连接焊盘。 当刀片在焊接掩模的顶部横向移动以填充焊接掩模中的开口时，液体焊料在受限制的空间中被分配到开口中。 然后将焊料材料固化以在开口中形成圆顶形焊料凸点。

Patent Agency Ranking