公开(公告)号：US06516513B2

公开(公告)日：2003-02-11

申请号：US10092117

申请日：2002-03-05

Applicant: Cynthia Susan Milkovich ,  Mark Vincent Pierson ,  Charles Gerard Woychik

Inventor： Cynthia Susan Milkovich ,  Mark Vincent Pierson ,  Charles Gerard Woychik

IPC: H05K336

CPC classification number: H05K3/4688 ,  H01L23/3735 ,  H01L23/49827 ,  H01L2224/05023 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/09701 ,  H05K1/0271 ,  H05K1/036 ,  H05K1/113 ,  H05K1/141 ,  H05K3/429 ,  H05K3/4641 ,  H05K2201/0133 ,  H05K2201/068 ,  H05K2201/10378 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus, material, such as a ceramic material, with a CTE closely matching the CTE of the chip. A second dielectric layer, on the laminate chip carrier side of the interposer, is made of resilient, low elastic modulus, material with metallurgy formed thereon, such as circuit board material, with a composite CTE closely matching the CTE of said chip carrier. A third dielectric intermediate layer, laminated between said first and second layers, is made of a low elastic modulus material with metallurgy formed thereon, such as a Teflon/glass particle material, with a composite CTE between the CTEs of said first and second layers.

公开(公告)号：US6156165A

公开(公告)日：2000-12-05

申请号：US421374

申请日：1999-10-20

Applicant: Mark Vincent Pierson ,  Thurston Bryce Youngs, Jr.

Inventor： Mark Vincent Pierson ,  Thurston Bryce Youngs, Jr.

IPC: H01L21/60 ,  H01L23/367 ,  H01L23/44 ,  H01L23/473 ,  H01L23/482 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K7/20 ,  C23C14/34 ,  B05D1/18 ,  C23C4/08 ,  C23C16/00 ,  H01L21/31

CPC classification number: H01L25/0657 ,  H01L23/3675 ,  H01L23/473 ,  H01L23/482 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/0002

Abstract: An integrated circuit package derives increased mechanical robustness and electrical reliability consistent with increased heat dissipation capacity by edge bonding of integrated circuit chips onto a substrate such as a chip, board, module or another integrated circuit by forming a solder or conductive adhesive bond between a bonding/contact pad on the substrate and a metallization feature extending at least on limited opposing areas of major surfaces of the chip and, preferably, across the edge of the chip. Thermally conducting material contained in a cap may provide additional, distributed support for the chip by a combination of viscosity and density providing buoyancy of the chips. Alternatively, a cap may be provided which further stabilizes the edge-mounting of chips while increasing velocity of cooling fluid against the chips. Novel techniques of forming a metallization feature across the edge of a chip with high efficiency and manufacturing yield includes enclosure of chips or strips of chips in a tool including a grooved mask or enclosing the chips or strips of chips in a resist which may be exposed and developed using at least a portion of the same tool.

Abstract translation: 集成电路封装通过在诸如芯片，板，模块或另一集成电路之类的衬底（例如芯片，板，模块或另一集成电路）上边缘焊接来形成增强的散热能力，从而提高了机械稳定性和电气可靠性。 /接触焊盘和金属化特征，其至少在芯片的主要表面的有限的相对区域上延伸，并且优选地跨越芯片的边缘延伸。 容纳在盖中的导热材料可以通过提供芯片浮力的粘度和密度的组合来为芯片提供附加的分布式支撑。 或者，可以提供帽，其进一步稳定了片的边缘安装，同时增加了对芯片的冷却流体的速度。 在高效率和制造成品率的跨芯片边缘形成金属化特征的新技术包括在工具中包括芯片或芯片条，其包括带槽的掩模或将可能暴露的抗蚀剂中的芯片或条带包围， 使用相同工具的至少一部分开发。

公开(公告)号：US6027006A

公开(公告)日：2000-02-22

申请号：US103864

申请日：1998-06-24

Applicant: Mark Vincent Pierson

Inventor： Mark Vincent Pierson

IPC: B23K3/06 ,  H05K1/00 ,  H05K3/00 ,  H05K3/12 ,  H05K3/34 ,  B23K3/00

CPC classification number: H05K3/3484 ,  B23K3/0623 ,  B23K3/0638 ,  H05K3/1225 ,  H05K3/3478 ,  B23K2201/36 ,  B23K2201/42 ,  H05K1/0393 ,  H05K2203/0126 ,  H05K2203/041 ,  H05K2203/043 ,  H05K2203/0557 ,  H05K2203/1545 ,  H05K3/0097 ,  H05K3/1216

Abstract: A method and apparatus is disclosed for applying solder to a substrate which has a predetermined pattern of receiving pads thereon and forming solder balls from the applied solder. A conveyor is provided having a support member and a continuous metering member. The metering member has openings thereon arranged in the same preselected pattern as the solder receiving pads on the substrate. The substrate is moved into contact with the support member and the metering member, the openings in the metering member being in alignment with the solder receiving pads of the substrate. A container of solder is provided which supplies solder to the openings. The solder may be in liquid form, or in paste form, or in the form of solid solder balls. The applied solder, if in the form of paste or solid balls is melted. Thereafter, the solder is solidified on the pads to form solder balls, and the substrate is discharged from the conveyor with the solidified solder balls thereon.

Abstract translation: 公开了一种用于将焊料施加到其上具有预定图案的接收焊盘并且从所施加的焊料形成焊球的衬底的方法和装置。 提供具有支撑构件和连续计量构件的输送机。 计量构件具有与基板上的焊料接收垫相同的预选图案布置的开口。 衬底移动与支撑构件和计量构件接触，计量构件中的开口与衬底的焊料接收衬垫对齐。 提供了一种焊料容器，其向开口提供焊料。 焊料可以是液体形式，或以糊状形式，或以固体焊球的形式。 所施加的焊料，如果以糊状物或固体球的形式熔化。 此后，焊料在焊盘上固化以形成焊球，并且基板从其上的固化的焊球从输送机排出。

公开(公告)号：US5808710A

公开(公告)日：1998-09-15

申请号：US835196

申请日：1997-04-07

Applicant: Mark Vincent Pierson

Inventor： Mark Vincent Pierson

IPC: G02F1/1347 ,  G02F1/13 ,  G02F1/1333 ,  G02F1/1345 ,  G09F9/40

CPC classification number: G02F1/13336 ,  G02F1/1345 ,  G02F1/13452

Abstract: Adjacent liquid crystal display tiles are internally electrically interconnected, thereby providing wire escapes for the pixels of the tiles.

Abstract translation: 相邻的液晶显示瓦片内部电互连，从而为瓦片的像素提供绕线。

公开(公告)号：US06946329B2

公开(公告)日：2005-09-20

申请号：US10832845

申请日：2004-04-27

Applicant: Mark Vincent Pierson ,  Jennifer Rebecca Sweterlitsch ,  Charles Gerard Woychik ,  Thurston Bryce Youngs, Jr.

Inventor： Mark Vincent Pierson ,  Jennifer Rebecca Sweterlitsch ,  Charles Gerard Woychik ,  Thurston Bryce Youngs, Jr.

IPC: H01L23/498 ,  H01R13/24 ,  H05K3/34 ,  H05K3/42 ,  H05K7/10 ,  H05K13/04 ,  H01L21/60 ,  H05K1/02

CPC classification number: H01R12/52 ,  H01L23/49827 ,  H01L2924/0002 ,  H01R12/57 ,  H01R13/2414 ,  H05K3/3436 ,  H05K3/42 ,  H05K7/1061 ,  H05K13/0465 ,  H05K2201/0133 ,  H05K2201/09836 ,  H05K2201/10378 ,  Y02P70/613 ,  Y10T29/49124 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A flexible, compliant layer of a single low modulus material for connecting a chip die directly to a circuit card without encapsulation. The flexible compliant layer provides stress relief caused by CTE thermal mismatch in chip die and circuit card. An array of copper plated vias are formed in said compliant layer with each via terminating on opposing surfaces of the layer in copper pads. Rather than copper, other metals, such as gold or nickel, may also be used. An array of holes may be positioned between said array of vias to provide additional resiliency. The plated vias may be angled with respect to said opposing surfaces to allow additional vertical and horizontal stress relief. Connection of the pads on one surface to high melt C-4 solder balls or columns on a chip die results in solder filled vias. Low melt solder connection of the pads on the other surface to a circuit card allows non-destructive rework of the cards.

Abstract translation: 用于将芯片裸片直接连接到电路卡而不封装的单个低模量材料的柔性兼容层。 灵活的柔性层提供了芯片和电路卡中CTE热失配引起的应力消除。 在所述顺应层中形成镀铜通孔的阵列，每个通孔终止于铜衬垫的相对表面上。 而不是铜，也可以使用其他金属，例如金或镍。 一组孔可以位于所述通孔阵列之间以提供额外的弹性。 电镀通孔可以相对于所述相对的表面成角度，以允许额外的垂直和水平应力释放。 将一个表面上的焊盘与芯片模具上的高熔点C-4焊球或柱的连接导致焊料填充的通孔。 将另一个表面上的焊盘的低熔点焊接连接到电路卡允许卡的非破坏性返修。

公开(公告)号：US6059939A

公开(公告)日：2000-05-09

申请号：US225316

申请日：1999-01-05

Applicant: Mark Vincent Pierson ,  Thurston Bryce Youngs, Jr.

Inventor： Mark Vincent Pierson ,  Thurston Bryce Youngs, Jr.

IPC: H01L21/60 ,  H01L23/367 ,  H01L23/44 ,  H01L23/473 ,  H01L23/482 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K7/20 ,  C23C14/34 ,  B05D1/18 ,  C23C4/08 ,  C23C16/00 ,  H01L21/31

CPC classification number: H01L25/0657 ,  H01L23/3675 ,  H01L23/473 ,  H01L23/482 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/0002

Abstract: An integrated circuit package derives increased mechanical robustness and electrical reliability consistent with increased heat dissipation capacity by edge bonding of integrated circuit chips onto a substrate such as a chip, board, module or another integrated circuit by forming a solder or conductive adhesive bond between a bonding/contact pad on the substrate and a metallization feature extending at least on limited opposing areas of major surfaces of the chip and, preferably, across the edge of the chip. Thermally conducting material contained in a cap may provide additional, distributed support for the chip by a combination of viscosity and density providing buoyancy of the chips. Alternatively, a cap may be provided which further stabilizes the edge-mounting of chips while increasing velocity of cooling fluid against the chips. Novel techniques of forming a metallization feature across the edge of a chip with high efficiency and manufacturing yield includes enclosure of chips or strips of chips in a tool including a grooved mask or enclosing the chips or strips of chips in a resist which may be exposed and developed using at least a portion of the same tool.

Abstract translation: 集成电路封装通过在诸如芯片，板，模块或另一集成电路之类的衬底（例如芯片，板，模块或另一集成电路）上边缘焊接来形成增强的散热能力，从而提高了机械稳定性和电可靠性， /接触焊盘和金属化特征，其至少在芯片的主要表面的有限的相对区域上延伸，并且优选地跨越芯片的边缘延伸。 容纳在盖中的导热材料可以通过提供芯片浮力的粘度和密度的组合来为芯片提供附加的分布式支撑。 或者，可以提供帽，其进一步稳定了片的边缘安装，同时增加了对芯片的冷却流体的速度。 在高效率和制造成品率的跨芯片边缘形成金属化特征的新技术包括在工具中包括芯片或芯片条，其包括带凹槽的掩模或将芯片或条带包围在可能暴露的抗蚀剂中， 使用相同工具的至少一部分开发。

公开(公告)号：US5818697A

公开(公告)日：1998-10-06

申请号：US828205

申请日：1997-03-21

Applicant: Gregg Joseph Armezzani ,  Robert Nicholas Ives ,  Mark Vincent Pierson ,  Terry Alan Tull

Inventor： Gregg Joseph Armezzani ,  Robert Nicholas Ives ,  Mark Vincent Pierson ,  Terry Alan Tull

IPC: H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H05K1/00 ,  H05K1/11 ,  H05K3/00 ,  H05K3/34 ,  H05K1/14

CPC classification number: H05K1/112 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49894 ,  H05K3/3452 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/12044 ,  H05K1/0393 ,  H05K2201/0989 ,  H05K2201/10734 ,  H05K2203/041 ,  H05K2203/0455 ,  H05K2203/1394 ,  H05K2203/1572 ,  H05K3/0094 ,  H05K3/3457 ,  H05K3/3478

Abstract: An electronic package is provided that includes a flexible polyimide film carrier having electronic circuitry on both of its major surfaces and a plurality of solder interconnection pads on a first major surface; solder mask layers located on both major surfaces, provided that areas between subsequently to be applied individual circuit chips on the first major surface exist that are free from the solder mask; and a plurality of modules attached to the film carrier by the solder balls or bumps. Also provided is a method for fabricating the electronic package that includes reflow of the solder balls or bumps to achieve attachment of the modules.

Abstract translation: 提供了一种电子封装，其包括在其主要表面上具有电子电路的柔性聚酰亚胺膜载体和在第一主表面上的多个焊料互连焊盘; 焊接掩模层位于两个主表面上，只要在第一主表面上随后施加单个电路芯片之间的区域就不存在焊接掩模; 以及通过焊球或凸起附接到胶片载体的多个模块。 还提供了一种用于制造电子封装的方法，其包括焊球或凸块的回流以实现模块的附接。

公开(公告)号：US5659256A

公开(公告)日：1997-08-19

申请号：US601923

申请日：1996-02-15

Applicant: Richard Gordon Charlton ,  George Charles Correia ,  Mark Andrew Couture ,  Gary Ray Hill ,  Kibby Barth Horsford ,  Anthony Paul Ingraham ,  Michael David Lowell ,  Voya Rista Markovich ,  Gordon Charles Osborne, Jr. ,  Mark Vincent Pierson

Inventor： Richard Gordon Charlton ,  George Charles Correia ,  Mark Andrew Couture ,  Gary Ray Hill ,  Kibby Barth Horsford ,  Anthony Paul Ingraham ,  Michael David Lowell ,  Voya Rista Markovich ,  Gordon Charles Osborne, Jr. ,  Mark Vincent Pierson

IPC: G01R1/04 ,  G01R1/073 ,  G01R31/28

CPC classification number: G01R1/0483 ,  G01R1/07307 ,  G01R31/2863 ,  G01R31/2886

Abstract: A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.

公开(公告)号：US06664637B2

公开(公告)日：2003-12-16

申请号：US09756062

申请日：2001-01-08

Applicant: Miguel Angel Jimarez ,  Cynthia Susan Milkovich ,  Mark Vincent Pierson

Inventor： Miguel Angel Jimarez ,  Cynthia Susan Milkovich ,  Mark Vincent Pierson

IPC: H01L2306

CPC classification number: H01L24/12 ,  B23K1/0016 ,  B23K2101/42 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/10126 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81013 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/351 ,  H05K3/0032 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10977 ,  H05K2201/10992 ,  H05K2203/0415 ,  H05K2203/043 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2924/00014

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a conductive structure that couples a first substrate to a second substrate. The first substrate may include a chip or a module. The second substrate may include a chip carrier or a circuit card. Thus, the present invention encompasses such coupling as chip to chip carrier, chip to circuit card, and module to circuit card. The conductive structure includes a first conductive body and a second conductive body. The first conductive body is attached to the first substrate and the second conductive body is attached to the second substrate. The first conductive body may include a solder bump, while the second conductive body may include a eutectic alloy, such as a eutectic alloy lead and tin. Alternatively, the second conductive body may include a non-eutectic alloy whose melting point is below the melting point of the first conductive body. A portion of the first conductive body is coated with a material that is nonsolderable and nonconductive. The melting point of the first conductive body is higher than the melting point of the second conductive body. The first and second conductive bodies are coupled mechanically and electrically by surface adhesion at an uncoated surface of the first conductive body. The adhesive coupling results from application of a temperature that lies between the melting points of the first and second conductive bodies.

Abstract translation: 电结构和相关联的制造方法，用于减少将第一衬底耦合到第二衬底的导电结构中的热诱导应变。 第一衬底可以包括芯片或模块。 第二衬底可以包括芯片载体或电路卡。 因此，本发明包括诸如芯片到芯片载体，芯片到电路卡以及模块到电路卡的耦合。 导电结构包括第一导电体和第二导电体。 第一导电体附接到第一基板，第二导电体附接到第二基板。 第一导电体可以包括焊料凸块，而第二导电体可以包括共晶合金，例如共晶合金铅和锡。 或者，第二导电体可以包括其熔点低于第一导电体的熔点的非共晶合金。 第一导电体的一部分涂覆有不可焊接和不导电的材料。 第一导电体的熔点高于第二导电体的熔点。 第一和第二导电体通过在第一导电体的未涂覆表面处的表面粘附机械和电连接。 通过施加位于第一和第二导电体的熔点之间的温度，产生粘合剂偶合。

公开(公告)号：US06295724B1

公开(公告)日：2001-10-02

申请号：US09428750

申请日：1999-10-28

Applicant: Alan Harris Crudo ,  John Gillette Davis ,  Christian Robert Le Coz ,  Mark Vincent Pierson ,  Amit Kumar Sarkhel ,  Ajit Kumar Trivedi

Inventor： Alan Harris Crudo ,  John Gillette Davis ,  Christian Robert Le Coz ,  Mark Vincent Pierson ,  Amit Kumar Sarkhel ,  Ajit Kumar Trivedi

IPC: B23P1900

CPC classification number: H05K3/3436 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/0047 ,  H05K3/225 ,  H05K3/341 ,  H05K3/429 ,  H05K2201/0949 ,  H05K2201/10287 ,  H05K2201/10734 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/175 ,  Y02P70/613 ,  Y10T29/49124 ,  Y10T29/49139 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49153 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49723 ,  Y10T29/49726 ,  Y10T29/49728 ,  Y10T29/4973 ,  Y10T29/49734 ,  Y10T29/49815 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53274

Abstract: A method and apparatus for efficiently repairing or reworking a printed circuit board having a solder ball grid array thereon efficiently and at minimum cost includes the steps of drilling out a plated-through hole to sever electrical connections between a ball grid array pad on one surface of the printed circuit board and internal circuits and circuits on an opposite surface of the printed circuit board; inserting a pin having an insulated sleeve surrounding a portion thereof into the drilled-out hole, the pin having attached to one end a wire for attachment to the ball grid array on one surface of the printed circuit board and a post at the other end of the pin for attachment of a wire to the post; the pin having a stop along its length to control vertical positioning of the pin in the drilled-out hole, the pin referred to as a via replacement (VR) pin. Alternately, after the plated through hole is drilled out, an insulated wire may be inserted into the hole with insulation removed from the length of the wire which extends beyond one surface of the printed circuit board. The bare length of wire is bent parallel to the surface of the printed circuit board and attached thereto by a solder reflow process. In a dog bone configuration, the wire is formed around a pad on the surface of the printed circuit board which receives the solder ball.

Abstract translation: 一种用于有效地修复或重新加工具有焊球栅格阵列的印刷电路板的方法和装置，其有效和最小的成本包括以下步骤：钻出电镀通孔以切断在一个表面上的球栅阵列垫之间的电连接 印刷电路板和印刷电路板的相对表面上的内部电路和电路; 将具有围绕其一部分的绝缘套筒的销插入钻出孔中，该销已经在一端附接有用于连接到印刷电路板的一个表面上的球栅阵列的导线，另一端的柱 用于将电线附接到柱的销; 该销具有沿其长度的止动件，以控制销在钻孔中的垂直定位，该引脚被称为通孔更换（VR）引脚。 或者，在电镀通孔被钻出之后，绝缘电线可以插入孔中，绝缘体从延伸超出印刷电路板的一个表面的导线的长度去除。 线的裸露长度平行于印刷电路板的表面弯曲并通过焊料回流工艺附着在其上。 在狗骨构造中，线形成在接收焊球的印刷电路板的表面上的焊盘周围。