公开(公告)号：US20180316374A1

公开(公告)日：2018-11-01

申请号：US16029432

申请日：2018-07-06

Applicant: QUALCOMM Incorporated

Inventor： Changhan Yun ,  Chengjie Zuo ,  Mario Velez ,  Niranjan Sunil Mudakatte ,  Shiqun Gu ,  Jonghae Kim ,  David Berdy

IPC: H04B1/16 ,  H01L49/02 ,  H01L23/522 ,  H01L23/00 ,  H01L27/01 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H04B1/00

CPC classification number: H04B1/1638 ,  H01F17/0013 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5223 ,  H01L23/64 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L27/01 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6616 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2223/6688 ,  H01L2224/04105 ,  H01L2224/24195 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H04B1/006 ,  H05K1/165 ,  H05K1/185 ,  H05K3/4605 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/097 ,  H05K2201/09827

Abstract: In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.

公开(公告)号：US09941156B2

公开(公告)日：2018-04-10

申请号：US14676728

申请日：2015-04-01

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Vidhya Ramachandran ,  Christine Sung-An Hau-Riege ,  John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Jihong Choi ,  Jun Chen ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295

Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.

公开(公告)号：US09596768B2

公开(公告)日：2017-03-14

申请号：US14196481

申请日：2014-03-04

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Jae Sik Lee ,  Shiqun Gu

IPC: H05K3/42 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K3/426 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L2224/18 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/111 ,  H05K1/115 ,  H05K3/0094

Abstract: A substrate includes a plurality of vias that are lined with dielectric polymer having a substantially uniform thickness. This substantial uniform thickness provides a lumen within each dielectric-polymer-layer-lined via that is substantially centered within the via. Subsequent deposition of metal into the lumen for each dielectric-polymer-layer-lined via thus provides conductive vias having substantially centered metal conductors.

Abstract translation: 衬底包括多个具有基本上均匀厚度的介电聚合物的通孔。 这个基本上均匀的厚度提供了在每个介质聚合物层衬里的通孔内的管腔，其基本上位于通孔内。 因此，随后将金属沉积到每个介质聚合物层衬里的通孔的内腔中，由此提供具有基本中心的金属导体的导电通孔。

公开(公告)号：US20160293475A1

公开(公告)日：2016-10-06

申请号：US14676728

申请日：2015-04-01

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Vidhya Ramachandran ,  Christine Sung-An Hau-Riege ,  John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Jihong Choi ,  Jun Chen ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295

Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.

Abstract translation: 公开了减小寄生电容的装置和方法。 器件可以包括电介质层。 该器件可以包括第一和第二导电结构以及靠近电介质层的蚀刻停止层。 蚀刻停止层可以限定靠近第一和第二导电结构之间的电介质层的区域的第一和第二开口。 该装置可以包括区域内的第一和第二气隙。 该装置可以包括靠近蚀刻停止层（例如，在上方，上方或上方）的材料层。 靠近蚀刻停止层的材料层可以覆盖第一和第二气隙。

公开(公告)号：US09368450B1

公开(公告)日：2016-06-14

申请号：US14832363

申请日：2015-08-21

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Hong Bok We ,  Jae Sik Lee ,  Dong Wook Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538

CPC classification number: H01L23/5385 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An integrated device package includes a first die, a second die, an encapsulation portion coupled to the first die and the second die, and a redistribution portion coupled to the encapsulation portion. The encapsulation portion includes an encapsulation layer, a bridge, and a first via. The bridge is at least partially embedded in the encapsulation layer. The bridge is configured to provide a first electrical path for a first signal between the first die and the second die. The first via is in the encapsulation layer. The first via is coupled to the bridge. The first via and the bridge are configured to provide a second electrical path for a second signal to the first die. The redistribution portion includes at least one dielectric layer, and at least one interconnect, in the dielectric layer, coupled to the first via.

Abstract translation: 集成器件封装包括第一管芯，第二管芯，耦合到第一管芯和第二管芯的封装部分，以及耦合到封装部分的再分配部分。 封装部分包括封装层，桥和第一通孔。 该桥至少部分地嵌入在封装层中。 桥被配置成为第一管芯和第二管芯之间的第一信号提供第一电路径。 第一个通道在封装层中。 第一个通道耦合到桥。 第一通孔和桥被配置为为第一模具提供第二信号的第二电路径。 再分配部分包括耦合到第一通孔的介电层中的至少一个电介质层和至少一个互连。

公开(公告)号：US20160013180A1

公开(公告)日：2016-01-14

申请号：US14856873

申请日：2015-09-17

Applicant: QUALCOMM Incorporated

Inventor： Rongtian Zhang ,  Lew Chua-Eoan ,  Shiqun Gu

IPC: H01L27/06 ,  H01L49/02 ,  H01L27/088

CPC classification number: H01L27/0629 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L27/13 ,  H01L28/86 ,  H01L29/66795

Abstract: A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate. The capacitor further includes a dielectric layer disposed onto the fin. The capacitor still further includes a second terminal having a FinFET compatible high-K metal gate disposed proximate and adjacent to the fin.

Abstract translation: 电容器包括半导体衬底。 电容器还包括具有设置在半导体衬底的表面上的翅片的第一端子。 电容器还包括设置在鳍片上的电介质层。 电容器还包括具有FinFET兼容的高K金属栅极的第二端子，该金属栅极靠近并邻近鳍片。

公开(公告)号：US20150333053A1

公开(公告)日：2015-11-19

申请号：US14805745

申请日：2015-07-22

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Brian Matthew Henderson ,  Shiqun Gu ,  Chiew-Guan Tan ,  Jung Pill Kim ,  Taehyun Kim

IPC: H01L27/02 ,  H01L23/48 ,  H01L29/66 ,  H01L21/304 ,  H01L29/861 ,  H01L21/762 ,  H01L29/06 ,  H01L27/08 ,  H01L21/768 ,  H01L29/872

CPC classification number: H01L29/66128 ,  H01L21/304 ,  H01L21/762 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/535 ,  H01L23/60 ,  H01L25/0657 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/0694 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/66143 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

Abstract translation: 一种方法包括使衬底的背面变薄以暴露形成在衬底中的第一通孔的一部分。 该方法还包括在衬底的背面形成第一二极管。 第一二极管耦合到第一通孔。

公开(公告)号：US20150318262A1

公开(公告)日：2015-11-05

申请号：US14324136

申请日：2014-07-04

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ratibor Radojcic ,  Dong Wook Kim ,  Jae Sik Lee

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L21/568 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/145 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/171 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81895 ,  H01L2224/81896 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/1434 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/18161 ,  H05K3/4688 ,  H01L2924/014

Abstract: Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (e.g., first wafer level die), and a second die (e.g., second wafer level die). The base portion includes a first inorganic dielectric layer, a first set of interconnects located in the first inorganic dielectric layer, a second dielectric layer different from the first inorganic dielectric layer, and a set of redistribution metal layers in the second dielectric layer. The first die is coupled to a first surface of the base portion. The second die is coupled to the first surface of the base portion, the second die is electrically coupled to the first die through the first set of interconnects.

Abstract translation: 一些新颖的特征涉及集成器件（例如，集成封装），其包括用于集成器件的基底部分，第一管芯（例如，第一晶片级管芯）和第二管芯（例如，第二晶片级管芯）。 基部包括第一无机电介质层，位于第一无机电介质层中的第一组互连，不同于第一无机介电层的第二电介质层和第二介电层中的一组再分布金属层。 第一管芯耦合到基部的第一表面。 第二管芯耦合到基部的第一表面，第二管芯通过第一组互连件电耦合到第一管芯。

公开(公告)号：US20150235991A1

公开(公告)日：2015-08-20

申请号：US14254494

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ratibor Radojcic ,  Dong Wook Kim

IPC: H01L25/065 ,  H05K1/11 ,  H01L23/00 ,  H05K1/09 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L25/0655 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/17 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/1712 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H05K1/09 ,  H05K1/115 ,  H05K2201/09845 ,  H05K2201/10242 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00

Abstract: A bottom package substrate is provided that includes a plurality of metal posts that electrically couple through a die-side redistribution layer to a plurality of die interconnects. The metal posts and the die interconnects are plated onto a seed layer on the bottom package substrate.

Abstract translation: 提供了底部封装基板，其包括多个金属柱，其通过裸片侧再分配层电耦合到多个管芯互连。 金属柱和管芯互连电镀在底部封装衬底上的晶种层上。

公开(公告)号：US20150206837A1

公开(公告)日：2015-07-23

申请号：US14160448

申请日：2014-01-21

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ryan David Lane ,  Urmi Ray

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5227 ,  H01L21/76838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/19 ,  H01L28/10 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, a first metal redistribution layer coupled to one of the metal layers, and a second metal redistribution layer coupled to the first metal redistribution layer. The first and second metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the integrated device also includes a third metal redistribution layer. The third metal redistribution layer is coupled to the first and second metal redistribution layers. The third metal redistribution layer is a via. In some implementations, the first, second, and third metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the first, second, and third redistribution layers form a set of windings for the toroid inductor.

Abstract translation: 一些特征涉及集成器件，其包括衬底，耦合到衬底的几个金属层，耦合到衬底的几个电介质层，耦合到金属层中的一个的第一金属再分布层，以及耦合到衬底的第二金属再分配层 第一金属再分配层。 第一和第二金属再分布层被配置为在集成器件中作为环形电感器工作。 在一些实施方案中，集成器件还包括第三金属再分配层。 第三金属再分布层耦合到第一和第二金属再分配层。 第三金属再分配层是通孔。 在一些实施方案中，第一，第二和第三金属再分配层被配置为在集成器件中作为环形电感器工作。 在一些实施方案中，第一，第二和第三再分配层形成用于环形电感器的一组绕组。