公开(公告)号：US20190131261A1

公开(公告)日：2019-05-02

申请号：US16233218

申请日：2018-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Ming-Da Cheng ,  Mirng-Ji Lii ,  Meng-Tse Chen ,  Wei-Hung Lin

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  B23K35/00 ,  B23K35/02 ,  B23K35/22 ,  B23K35/26 ,  B23K35/36 ,  H01L25/10 ,  H01L21/56 ,  H01L25/00 ,  H01L25/03

CPC classification number: H01L24/05 ,  B23K35/001 ,  B23K35/0222 ,  B23K35/22 ,  B23K35/262 ,  B23K35/3613 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/3178 ,  H01L23/498 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/06181 ,  H01L2224/08113 ,  H01L2224/1184 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/1355 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13666 ,  H01L2224/1412 ,  H01L2224/14181 ,  H01L2224/16104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/013 ,  H01L2924/206 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.

公开(公告)号：US20160111385A1

公开(公告)日：2016-04-21

申请号：US14975911

申请日：2015-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Shi Liu ,  Ming-Da Cheng ,  Mirng-Ji Lii ,  Meng-Tse Chen ,  Wei-Hung Lin

IPC: H01L23/00 ,  B23K35/00 ,  B23K35/26 ,  B23K35/22 ,  B23K35/02 ,  B23K35/36

CPC classification number: H01L24/05 ,  B23K35/001 ,  B23K35/0222 ,  B23K35/22 ,  B23K35/262 ,  B23K35/3613 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/3178 ,  H01L23/498 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/06181 ,  H01L2224/08113 ,  H01L2224/1184 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/1355 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13666 ,  H01L2224/1412 ,  H01L2224/14181 ,  H01L2224/16104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/013 ,  H01L2924/206 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small.

Abstract translation: 形成封装封装（PoP）结构的机构的所述实施例包括将具有非焊料金属球的连接器与包装衬底结合。 非焊接金属球可以包括焊料涂层。 具有非焊接金属球的连接器可以基本保持连接器的形状并控制上部和下部封装之间的结合结构的高度。 具有非焊接金属球的连接器也不太可能导致连接器之间的桥接或接合连接器的断开（或冷接头）。 结果，可以将具有非焊接金属球的连接器的间距保持较小。

公开(公告)号：US20250166895A1

公开(公告)日：2025-05-22

申请号：US19027577

申请日：2025-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Hung-Yi Kuo ,  Nien-Fang Wu

IPC: H01F41/04 ,  H01F17/00 ,  H01L23/522 ,  H01L23/525

Abstract: A system and method for providing and programming a programmable inductor is provided. The structure of the programmable inductor includes multiple turns, with programmable interconnects incorporated at various points around the turns to provide a desired isolation of the turns during programming. In an embodiment the programming may be controlled using the size of the vias, the number of vias, or the shapes of the interconnects.

公开(公告)号：US20250149485A1

公开(公告)日：2025-05-08

申请号：US19013241

申请日：2025-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Yung-Ching Chao ,  Chun Kai Tzeng ,  Cheng Jen Lin ,  Chin Wei Kang ,  Yu-Feng Chen ,  Mirng-Ji Lii

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/488 ,  H01L23/522

Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.

公开(公告)号：US12136644B2

公开(公告)日：2024-11-05

申请号：US18063339

申请日：2022-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Kai Tzeng ,  Cheng Jen Lin ,  Yung-Ching Chao ,  Ming-Da Cheng ,  Mirng-Ji Lii

IPC: H01L23/522 ,  H01L21/311 ,  H01L49/02

Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.

公开(公告)号：US20240266304A1

公开(公告)日：2024-08-08

申请号：US18637539

申请日：2024-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao Chun Liu ,  Ching-Wen Hsiao ,  Kuo-Ching Hsu ,  Mirng-Ji Lii

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/585 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/35121

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.

公开(公告)号：US11742204B2

公开(公告)日：2023-08-29

申请号：US17316008

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jung Hsueh ,  Chen-En Yen ,  Chin Wei Kang ,  Kai Jun Zhan ,  Wei-Hung Lin ,  Cheng Jen Lin ,  Ming-Da Cheng ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32135 ,  H01L21/32139

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

公开(公告)号：US20230253369A1

公开(公告)日：2023-08-10

申请号：US18302496

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Lee ,  Tsung-Ding Wang ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L21/78 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L24/97 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/49827 ,  H01L24/00 ,  H01L21/563 ,  H01L21/78 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L23/3128

Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

公开(公告)号：US11652086B2

公开(公告)日：2023-05-16

申请号：US17087106

申请日：2020-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Lee ,  Tsung-Ding Wang ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L21/78 ,  H01L25/18 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/49827 ,  H01L24/00 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L23/3128 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

公开(公告)号：US11594484B2

公开(公告)日：2023-02-28

申请号：US16915312

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mirng-Ji Lii ,  Chung-Shi Liu ,  Chin-Yu Ku ,  Hung-Jui Kuo ,  Alexander Kalnitsky ,  Ming-Che Ho ,  Yi-Wen Wu ,  Ching-Hui Chen ,  Kuo-Chio Liu

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.