公开(公告)号：US20110006415A1

公开(公告)日：2011-01-13

申请号：US12501686

申请日：2009-07-13

申请人： Mark A. Bachman ,  John W. Osenbach ,  Kishor V. Desai

发明人： Mark A. Bachman ,  John W. Osenbach ,  Kishor V. Desai

IPC分类号： H01L23/52 ,  H01L21/60 ,  H01L23/488

CPC分类号： H01L24/11 ,  H01L21/4853 ,  H01L21/4867 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/1132 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/13647 ,  H01L2224/16 ,  H01L2224/16503 ,  H01L2224/81399 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01063 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/81455 ,  H01L2224/13099 ,  H01L2224/05552

摘要： A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process.

摘要翻译： 形成电子器件的方法提供了一种具有位于其上的焊料凸块垫的电子器件衬底。 含镍层位于焊料凸块上。 在使电子器件进行回流处理之前，在含镍层上形成含铜层。

公开(公告)号：US06272742B1

公开(公告)日：2001-08-14

申请号：US09415330

申请日：1999-10-08

申请人： Gregg J. Armezzani ,  Kishor V. Desai ,  Jeffery S. Perkins ,  John J. Pessarchick

发明人： Gregg J. Armezzani ,  Kishor V. Desai ,  Jeffery S. Perkins ,  John J. Pessarchick

IPC分类号： H05K336

CPC分类号： H05K1/112 ,  H05K1/0298 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144

摘要： A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of placing one or more blind vias in a first substrate positioned on top of a first conductor; placing one or more blind vias in a second substrate positioned under a second conductor; attaching one or more signal lines to one or more of the one or more blind vias; and assembling ball grid array components such that the first conductor is electrically connected to the second conductor. Also claimed is an electronic circuit package incorporating the blind vias for electrical connection between layers in accordance with the present invention.

摘要翻译： 提供了一种用于连接电子电路封装中的两个导电层的方法，包括以下步骤：将一个或多个盲孔放置在位于第一导体顶部的第一衬底中; 将一个或多个盲孔放置在位于第二导体下方的第二衬底中; 将一个或多个信号线附接到所述一个或多个盲孔中的一个或多个; 以及组装球栅阵列部件，使得第一导体电连接到第二导体。 还要求保护的是一种电子电路封装，其包括用于根据本发明的层之间的电连接的盲孔。

公开(公告)号：US06224396B1

公开(公告)日：2001-05-01

申请号：US09329537

申请日：1999-06-10

申请人： Benson Chan ,  Kishor V. Desai ,  John H. Sherman

发明人： Benson Chan ,  Kishor V. Desai ,  John H. Sherman

IPC分类号： H01R1200

CPC分类号： H05K7/1069 ,  H01R12/52 ,  H01R12/714 ,  H05K3/325

摘要： An interposer for connecting two circuit members. The interposer has two extending conductive ends, is “Z” shaped, and has a center of gravity positioned relative to one of the conductive ends such that the interposer is capable of standing upright upon that end without external support. The interposer may be composed of a plated metal, and at least one of the extending conductive ends may have deposited dendrites or a raised bump. The Z-shaped interposer prevents bowing or cracking of the connected structure which otherwise occurs during use due to the different thermal coefficients of expansion of the two circuit members.

摘要翻译： 用于连接两个电路部件的插入器。 插入器具有两个延伸的导电端，为“Z”形，并且具有相对于导电端之一定位的重心，使得插入件能够在该端部处直立而无需外部支撑。 插入器可以由电镀金属组成，并且至少一个延伸的导电端可以具有沉积的枝晶或凸起的凸起。 由于两个电路构件的不同的热膨胀系数，Z形插入件防止在使用期间发生的连接结构的弯曲或破裂。

公开(公告)号：US6166434A

公开(公告)日：2000-12-26

申请号：US935583

申请日：1997-09-23

申请人： Kishor V. Desai ,  Sunil A. Patel ,  John P. McCormick

发明人： Kishor V. Desai ,  Sunil A. Patel ,  John P. McCormick

IPC分类号： H01L21/56 ,  H01L23/04 ,  H01L23/12

CPC分类号： H01L21/563 ,  H01L23/04 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/0401

摘要： Provided is a die clip for use in semiconductor flip chip packaging as a replacement for the conventional combination of a heat spreader and stiffener, a packaging method using the die clip, and a semiconductor package incorporating the die clip. In a preferred embodiment, the die clip is a piece of high modulus, high thermal conductivity material shaped to attach over a die on the surface of a packaging substrate. The die clip closely engages the die while leaving some space open around the perimeter to provide access to the die. An underfill material may then be dispensed into the gap between the die and the substrate through an opening in the die clip. The underfill material is then cured, the die clip providing a heat sink and keeping the die and substrate flat and immobile during and after the curing process. A BGA process may then be used to apply solder balls to the underside of the substrate for subsequent bonding of the package to a circuit board for use.

摘要翻译： 提供了一种用于半导体倒装芯片封装的芯片夹，作为热扩散器和加强件的常规组合的替代品，使用该芯片夹的封装方法以及并入该夹具的半导体封装。 在一个优选实施例中，模夹是一片高模量，高导热性的材料，其被成形为附着在包装基底的表面上的模具上。 模夹紧密地接合模具，同时在周边周围留出一些空间以提供对模具的接近。 然后可以通过模夹中的开口将底部填充材料分配到模具和基板之间的间隙中。 然后固化底部填充材料，模具夹提供散热器并且在固化过程中和之后使模具和基底保持平坦且不变。 然后可以使用BGA工艺将焊球施加到衬底的下侧，以便随后将封装连接到电路板以供使用。

公开(公告)号：US6023029A

公开(公告)日：2000-02-08

申请号：US44966

申请日：1998-03-19

申请人： Gregg J. Armezzani ,  Kishor V. Desai ,  Jeffery S. Perkins ,  John J. Pessarchick

发明人： Gregg J. Armezzani ,  Kishor V. Desai ,  Jeffery S. Perkins ,  John J. Pessarchick

IPC分类号： H05K1/00 ,  H05K1/11 ,  H05K1/16

CPC分类号： H05K1/112 ,  H05K1/0298 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144

摘要： A method is provided for connecting two conductive layers in an electronic circuit package including the steps of placing one or more blind vias in a first substrate positioned on top of a first conductor; placing one or more blind vias in a second substrate positioned under a second conductor; attaching one or more signal lines to one or more of the one or more blind vias; and assembling ball grid array components such that the first conductor is electrically connected to the second conductor. Also claimed is an electronic circuit package incorporating the blind vias for electrical connection between layers in accordance with the present invention.

摘要翻译： 提供了一种用于连接电子电路封装中的两个导电层的方法，包括以下步骤：将一个或多个盲孔放置在位于第一导体顶部的第一衬底中; 将一个或多个盲孔放置在位于第二导体下方的第二衬底中; 将一个或多个信号线附接到所述一个或多个盲孔中的一个或多个; 以及组装球栅阵列部件，使得第一导体电连接到第二导体。 还要求保护的是一种电子电路封装，其包括用于根据本发明的层之间的电连接的盲孔。

公开(公告)号：US5604445A

公开(公告)日：1997-02-18

申请号：US360919

申请日：1994-12-21

申请人： Kishor V. Desai ,  Maganlal S. Patel ,  Sanjeev Sathe

发明人： Kishor V. Desai ,  Maganlal S. Patel ,  Sanjeev Sathe

IPC分类号： G01R1/04 ,  G01R31/28 ,  H01R4/58 ,  H05K5/00 ,  H01R9/09

CPC分类号： G01R31/2863 ,  G01R1/0483 ,  H01R4/58

摘要： An apparatus, and a corresponding method, for stress testing both wire bond-type semiconductor chips and C4-type semiconductor chips is disclosed.

摘要翻译： 公开了一种用于对线接合型半导体芯片和C4型半导体芯片进行应力测试的装置和相应的方法。

公开(公告)号：US5479703A

公开(公告)日：1996-01-02

申请号：US309777

申请日：1994-09-21

申请人： Kishor V. Desai ,  Harold Kohn ,  Richard C. Senger ,  Donald P. Seraphim

发明人： Kishor V. Desai ,  Harold Kohn ,  Richard C. Senger ,  Donald P. Seraphim

IPC分类号： B42D15/10 ,  G06K19/077 ,  H01L21/48 ,  H01L23/538 ,  H05K3/20 ,  H05K3/28 ,  H05K3/32 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H05K3/34

CPC分类号： H05K3/462 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5384 ,  H01L23/5385 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/10234 ,  H05K2203/0338 ,  H05K2203/0376 ,  H05K2203/063 ,  H05K3/20 ,  H05K3/205 ,  H05K3/28 ,  H05K3/328 ,  H05K3/4046 ,  H05K3/423 ,  H05K3/4623 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49165

摘要： A multi-layer printed circuit board or card including a plurality of circuitized power cores, the circuitized power cores include a layer of an electrically conductive material having a layer of electrically insulating material attached on both sides thereof. The circuitized power cores also include a plurality of plated through holes formed therethrough in substantially the same pattern on each circuitized power core. The circuitized power cores are parallel to each other such that corresponding plated through holes in the two circuitized power cores are co-linear. A plurality of substantially spherical balls are located between the circuitized power cores and are in contact with the corresponding plated through holes on facing cards. The balls have a diameter slightly larger than the opening of the plated through holes and are made of an electrically conductive material.

摘要翻译： 一种多层印刷电路板或卡片，包括多个电路化的电源核心，电路化的电源核心包括一层导电材料，其上具有一层电绝缘材料，该电绝缘材料层在其两侧。 电路化的功率核心还包括在每个电路化的功率核心上以基本上相同的图案形成的多个电镀通孔。 电路化的功率核心彼此平行，使得两个电路化的功率核心中相应的电镀通孔是共线的。 多个基本上球形的球位于电路化的功率核之间并且与相对的卡上的对应的电镀通孔接触。 球的直径略大于电镀通孔的开口，并且由导电材料制成。

公开(公告)号：US5259781A

公开(公告)日：1993-11-09

申请号：US977946

申请日：1992-11-18

申请人： John G. Baumberger ,  James R. Bentlage ,  Fletcher W. Chapin ,  Kishor V. Desai ,  Alan D. Knight ,  Thomas G. Macek

发明人： John G. Baumberger ,  James R. Bentlage ,  Fletcher W. Chapin ,  Kishor V. Desai ,  Alan D. Knight ,  Thomas G. Macek

IPC分类号： H01R12/71 ,  H01R13/24 ,  H01R13/621 ,  H05K7/10 ,  H01R13/627

CPC分类号： H01R13/2435 ,  H01R12/714 ,  H01R13/6215 ,  H05K7/1069

摘要： A connector assembly has a plurality of electrical circuit members and interposer frames with resilient contact members pressed together by a centrally located actuation screw. The actuation screw is supported within a threaded hole in an actuation bar on one side of one of the circuit members. Turning the actuation screw in its threaded hole causes various parts of the connector assembly to be pressed together simultaneously under an evenly distributed load. A load distribution plate located between the actuation screw and the nearest circuit member reduces the bending stresses in that circuit member. Alignment bushings and pins extending through openings in the circuit members maintain the various parts of the assembly in proper alignment while the actuation screw is being turned.

摘要翻译： 连接器组件具有多个电路构件和具有弹性接触构件的介入框架，弹性接触构件通过位于中心的致动螺钉压在一起。 致动螺钉被支撑在一个电路构件的一侧上的致动杆的螺纹孔内。 在其螺纹孔中转动致动螺钉使得连接器组件的各个部件在均匀分布的负载下同时被压在一起。 位于致动螺钉和最近的电路部件之间的负载分配板降低了该电路部件中的弯曲应力。 对准衬套和延伸穿过电路构件中的开口的销在保持致动螺丝转动的同时保持组件的各个部分正确对准。

公开(公告)号：US4788767A

公开(公告)日：1988-12-06

申请号：US24491

申请日：1987-03-11

申请人： Kishor V. Desai ,  Kohn Harold

发明人： Kishor V. Desai ,  Kohn Harold

IPC分类号： H01L23/50 ,  H01L21/98 ,  H01L23/32 ,  H01L23/498 ,  H01L23/538 ,  H01R43/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC分类号： H01L25/50 ,  H01L23/4985 ,  H01L23/5385 ,  H05K3/3436 ,  H05K3/363 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/207 ,  H01L2924/30107 ,  H05K1/141 ,  H05K2201/049 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2201/10477 ,  H05K2201/10681 ,  H05K2201/10704 ,  H05K2203/0415 ,  H05K2203/0769 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49144

摘要： A method and apparatus are disclosed for mounting a flexible film semiconductor chip carrier on a second level electronic package, such that the flexible film of the carrier is supported substantially in a plane above the surface of the second level electronic package. The method comprises positioning preformed spacers embedded in a dissolvable polysulfone foam holder between the outer lead bonding pads on the flexible film semiconductor chip carrier and corresponding (matching) bonding pads on the second level electronic package. Each of the preformed spacers may comprise, for example, a solder cylinder with a copper core. The preformed spacers may be bonded to the outer lead bonding pads on the chip carrier, and to the matching bonding pads on the second level electronic package, by reflowing the solder of the spacers using, for example, a conventional solder reflow oven. Then, the holder is dissolved, and washed away, in a conventional vapor degreaser using, for example, methylene chloride, to leave the flexible film semiconductor chip carrier mounted on the second level electronic package with the flexible film of the carrier having a planar geometry as desired.

公开(公告)号：US08378485B2

公开(公告)日：2013-02-19

申请号：US12501686

申请日：2009-07-13

申请人： Mark A. Bachman ,  John W. Osenbach ,  Kishor V. Desai

发明人： Mark A. Bachman ,  John W. Osenbach ,  Kishor V. Desai

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L21/4853 ,  H01L21/4867 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/1132 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/13647 ,  H01L2224/16 ,  H01L2224/16503 ,  H01L2224/81399 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01063 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/81455 ,  H01L2224/13099 ,  H01L2224/05552

摘要： A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process.