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    Universal integrated circuit programming socket board rewirable by means of an interconnect adapter board
    21.
    发明申请
    Universal integrated circuit programming socket board rewirable by means of an interconnect adapter board 审中-公开
    通用集成电路编程插座板可通过互连适配器板重新布线

    公开(公告)号：US20070111553A1

    公开(公告)日：2007-05-17

    申请号：US11273225

    申请日：2005-11-12

    Applicant: Richard Fleck

    Inventor： Richard Fleck

    IPC: H01R29/00 ,  G06F17/50

    CPC classification number: H05K1/029 ,  H01R12/515 ,  H01R13/465 ,  H01R29/00 ,  H05K1/141 ,  H05K3/222 ,  H05K2201/10325 ,  H05K2201/10704

    Abstract: A tool for programming integrated circuits which reduces redundancy of parts by making different and multiple programmable integrated circuit sockets of particular sizes and shapes adaptable to more than one programming cable, and therefore many different integrated circuits. By inserting a small interconnect adapter board onto the main programming board, it rewires the main board such that one or more of the included device programming sockets is connected properly to the correct in-system cable connector required by the manufacturer of the particular integrated circuit being programmed. Since the integrated circuit sockets are not permanently wired to a particular programming cable connector, the programming adapter is extremely versatile.

    Abstract translation: 用于编程集成电路的工具，其通过制造具有特定尺寸和形状的不同的和多个可编程集成电路插座来适应多于一个的编程电缆以及因此许多不同的集成电路来减少部件的冗余。 通过在主编程板上插入小型互连适配器板，它重新连接主板，使得一个或多个所包含的设备编程插座正确连接到特定集成电路的制造商所需的正确的系统中的电缆连接器 程序。 由于集成电路插座不是永久连接到特定的编程电缆连接器，所以编程适配器是非常通用的。

    Electronic package connected to a substrate
    23.
    发明申请
    Electronic package connected to a substrate 审中-公开
    电子封装连接到基板

    公开(公告)号：US20070002549A1

    公开(公告)日：2007-01-04

    申请号：US11173222

    申请日：2005-06-30

    Applicant: Patricia Brusso ,  Rhonda Higgins

    Inventor： Patricia Brusso ,  Rhonda Higgins

    IPC: H05K7/10 ,  H01L23/055

    CPC classification number: H05K3/3421 ,  H01R12/526 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/10333 ,  H05K2201/10704 ,  H05K2201/10962 ,  Y02P70/613

    Abstract: In some example embodiments, an electronic assembly includes a substrate and an electronic package. The substrate includes a hole that extends partially through the substrate. The electronic package includes a pin that extends from the electronic package. The pin is inserted into the hole that extends partially through the substrate. The substrate may be a motherboard that includes an upper surface and a lower surface with one or more conductive paths between the upper surface and the lower surface. The pin may engage at least one of the conductive paths. The pin and the hole may be any size, shape or geometry that permits the electronic package to be bonded to the motherboard. In addition, the hole may extend to any depth through the substrate as long as long the hole extends partially through the substrate and not all of the way through the substrate.

    Abstract translation: 在一些示例性实施例中，电子组件包括基板和电子封装。 衬底包括部分延伸穿过衬底的孔。 电子封装包括从电子封装延伸的销。 销插入到部分穿过基板的孔中。 衬底可以是包括上表面和下表面的母板，在上表面和下表面之间具有一个或多个导电路径。 销可以接合至少一个导电路径。 销和孔可以是允许电子封装结合到母板的任何尺寸，形状或几何形状。 此外，只要孔长度部分延伸穿过衬底，而不是全部通过衬底，孔可延伸到通过衬底的任何深度。

    Enhanced PGA interconnection
    26.
    发明申请
    Enhanced PGA interconnection 审中-公开
    增强型PGA互连

    公开(公告)号：US20060022327A1

    公开(公告)日：2006-02-02

    申请号：US10903749

    申请日：2004-07-30

    Applicant: Edgardo Hortaleza

    Inventor： Edgardo Hortaleza

    IPC: H01L23/48 ,  H01L21/50

    CPC classification number: H01L23/49811 ,  H01L2924/0002 ,  H05K3/3426 ,  H05K2201/10318 ,  H05K2201/10704 ,  Y02P70/613 ,  H01L2924/00

    Abstract: A pin grid array package, comprising a substrate, a chip mounted abutting said substrate, and a plurality of pins electrically connected to said substrate, each pin comprising a substantially flat disc at an end of the pin opposite the substrate, said disc oriented perpendicular to said pin. The substrate contains metal traces to transfer electrical signals between the chip and each pin, wherein said disc is usable to provide each pin an electrical connection to a structure external to the package.

    Abstract translation: 一种引脚格栅阵列封装，包括基板，安装在所述基板上的芯片，以及电连接到所述基板的多个引脚，每个引脚在与所述基板相对的所述引脚的端部处包括基本平坦的盘，所述盘垂直于 说针 衬底包含用于在芯片和每个引脚之间传送电信号的金属迹线，其中所述盘可用于向每个引脚提供与封装外部结构的电连接。

    Enhanced blind hole termination of pin to PCB
    28.
    发明申请
    Enhanced blind hole termination of pin to PCB 失效
    增强盲孔终端到PCB的引脚

    公开(公告)号：US20050263322A1

    公开(公告)日：2005-12-01

    申请号：US11179097

    申请日：2005-07-12

    Applicant: Scott Mickievicz ,  John Knaub

    Inventor： Scott Mickievicz ,  John Knaub

    IPC: H05K1/11 ,  H05K3/34 ,  H05K3/46 ,  H05K7/06

    CPC classification number: H05K1/112 ,  H05K3/3421 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10704 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

    Abstract: Tails (20) projecting from an electrical component (12) that lies on a circuit board surface, are terminated to traces on a multi-layer circuit board (14) in a manner that minimizes the disadvantages of long through hole soldering and of surface mount techniques. A blind hole is drilled and plated to form a shallow well (70). The well is filled with a soldering composition (130). A tail (20) is projected downward into the soldering composition with the extreme tip of the tail lying above the bottom of the hole, and the soldering composition is heated to solder the tail to the hole plating.

    Abstract translation: 从位于电路板表面的电气部件（12）突出的尾部（20）以多层电路板（14）的迹线端接，以最小化长通孔焊接和表面安装的缺点 技术 钻孔并镀上盲孔以形成浅井（70）。 该井装有焊接组合物（130）。 尾部（20）向下突出到焊接组合物中，尾部的最末端位于孔的底部之上，并且焊接组合物被加热以将尾部焊接到孔镀层。

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