公开(公告)号：US08420430B2

公开(公告)日：2013-04-16

申请号：US12769087

申请日：2010-04-28

申请人： Chi-Hsin Chiu ,  Chih-Ming Huang ,  Chang-Yueh Chan ,  Hsin-Yi Liao ,  Chun-Chi Ke

发明人： Chi-Hsin Chiu ,  Chih-Ming Huang ,  Chang-Yueh Chan ,  Hsin-Yi Liao ,  Chun-Chi Ke

IPC分类号： H01L21/56 ,  H01L21/60

CPC分类号： B81B7/0064 ,  B81B7/007 ,  B81B2207/095 ,  H01L21/56 ,  H01L23/315 ,  H01L23/552 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A fabrication method of a package structure having at least an MEMS element is provided, including: preparing a wafer having electrical connection pads and the at least an MEMS element; disposing lids for covering the at least an MEMS element, the lids having a metal layer formed thereon; electrically connecting the electrical connection pads and the metal layer with bonding wires; forming an encapsulant for covering the lids, bonding wires, electrical connection pads and metal layer; removing portions of the encapsulant to separate the bonding wires each into first and second sub-bonding wires, wherein top ends of the first and second sub-bonding wires are exposed, the first sub-bonding wires electrically connecting to the electrical connection pads, and the second sub-bonding wires electrically connecting to the metal layer; forming metallic traces on the encapsulant for electrically connecting to the first sub-bonding wires; forming bumps on the metallic traces; and performing a singulation process.

摘要翻译： 提供具有至少MEMS元件的封装结构的制造方法，包括：制备具有电连接焊盘和所述至少MEMS元件的晶片; 设置用于覆盖所述至少一个MEMS元件的盖，所述盖具有在其上形成的金属层; 电连接焊盘和金属层与接合线; 形成用于覆盖盖子，接合线，电连接垫和金属层的密封剂; 去除所述密封剂的部分以将所述接合线分别分离成第一和第二子接合线，其中所述第一和第二次接合线的顶端被暴露，所述第一子接合线电连接到所述电连接焊盘，以及 所述第二子接合线电连接到所述金属层; 在所述密封剂上形成用于电连接到所述第一子接合线的金属迹线; 在金属痕迹上形成凸块; 并执行单独处理。

公开(公告)号：US20110298126A1

公开(公告)日：2011-12-08

申请号：US12970126

申请日：2010-12-16

申请人： Yueh-Ying Tsai ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Yueh-Ying Tsai ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/492 ,  H01L23/488 ,  H01L21/50

CPC分类号： H01L23/49582 ,  H01L21/4832 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49548 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.

摘要翻译： 制造无载体半导体封装的方法包括：半蚀刻金属载体以形成多个凹槽和多个金属柱，每个金属柱用作焊盘或管芯焊盘的位置; 用第一密封剂填充每个凹槽; 在金属柱上形成诸如镀银层或有机可焊保护层的抗氧化层; 并分别进行芯片接合，引线接合和模制工艺以形成封装芯片的第二密封剂。 凹槽被第一密封剂填充以增强第一密封剂和金属载体之间的粘合性，从而解决了具有弱和柔韧的铜板的传统问题，并避免了运输困难。 本发明消除了使用昂贵的金属作为抗蚀剂层以降低制造成本，并且还允许导电迹线被柔性地布置在金属载体上以增强电连接质量。

公开(公告)号：US20110159643A1

公开(公告)日：2011-06-30

申请号：US12770059

申请日：2010-04-29

申请人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L21/60 ,  H01L21/56

CPC分类号： H01L23/495 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49117 ,  Y10T29/49171 ,  Y10T29/49172 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A fabrication method of a semiconductor package structure includes: patterning a metal plate having first and second surfaces; forming a dielectric layer on the metal plate; forming a metal layer on the first surface and the dielectric layer; forming metal pads on the second surface, the metal layer having a die pad and traces each having a bond pad; mounting a semiconductor chip on the die pad, followed by connecting electrically the semiconductor chip to the bond pads through bonding wires; forming an encapsulant to cover the semiconductor chip and the metal layer; removing portions of the metal plate not covered by the metal pads so as to form metal pillars; and performing a singulation process. The fabrication method is characterized by disposing traces with bond pads close to the die pad to shorten the bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging.

摘要翻译： 半导体封装结构的制造方法包括：图案化具有第一表面和第二表面的金属板; 在所述金属板上形成电介质层; 在所述第一表面和所述电介质层上形成金属层; 在所述第二表面上形成金属焊盘，所述金属层具有管芯焊盘并且各自具有接合焊盘; 将半导体芯片安装在芯片焊盘上，然后通过接合线将半导体芯片电连接到焊盘; 形成密封剂以覆盖半导体芯片和金属层; 去除未被金属垫覆盖的金属板的部分，以形成金属柱; 并执行单独处理。 该制造方法的特征在于，将具有接合焊盘的迹线设置在芯片焊盘附近以缩短接合线并形成从电介质层突出的金属柱，以避免焊料桥接。

公开(公告)号：US20110157851A1

公开(公告)日：2011-06-30

申请号：US12759117

申请日：2010-04-13

申请人： Pang-Chun Lin ,  Hsiao-Jen Hung ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Pang-Chun Lin ,  Hsiao-Jen Hung ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H05K7/02

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49165 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package structure includes a base body having a first encapsulant and a wiring layer embedded in and exposed from the first encapsulant. The wiring layer has a plurality of conductive traces and a plurality of first electrical contact pads. The first encapsulant has openings for exposing the first electrical contact pads, a chip electrically connected to the wiring layer, and a second encapsulant formed on the base body for covering the chip and the wiring layer, thereby providing an even surface for preventing the encapsulant from cracking when the chip is mounted.

摘要翻译： 封装结构包括具有第一密封剂和嵌入第一密封剂并暴露于第一密封剂的布线层的基体。 布线层具有多个导电迹线和多个第一电接触焊盘。 第一密封剂具有用于暴露第一电接触焊盘的开口，与布线层电连接的芯片，以及形成在基体上的用于覆盖芯片和布线层的第二密封剂，从而提供均匀的表面，以防止密封剂 芯片安装时开裂。

公开(公告)号：US20110156252A1

公开(公告)日：2011-06-30

申请号：US12859635

申请日：2010-08-19

申请人： Pang-Chun Lin ,  Chun-Yuan Li ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Pang-Chun Lin ,  Chun-Yuan Li ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/49 ,  H01L21/00

CPC分类号： H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/85001 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.

摘要翻译： 具有电连接结构的半导体封装包括：具有管芯焊盘和围绕管芯焊盘的迹线的导电层; 一个芯片 接合线; 具有多个空腔的密封剂，其深度大于管芯焊盘的厚度，以及用于将管芯焊盘和其中的迹线嵌入其中的迹线，以及暴露管芯焊盘和迹线的空腔; 形成在所述空腔中的焊料掩模层，并且具有用于暴露所述迹线端部和所述管芯焊盘的一部分的多个开口; 以及形成在开口中并电连接到迹线端的焊球。 将焊料掩模层与密封剂接合，增强了焊料掩模层的粘合强度，从而延长了水分渗透路径并提高了封装的可靠性。

公开(公告)号：US20110070728A1

公开(公告)日：2011-03-24

申请号：US12956393

申请日：2010-11-30

申请人： Chun-Chi Ke ,  Chien-Ping Huang

发明人： Chun-Chi Ke ,  Chien-Ping Huang

IPC分类号： H01L21/768

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/013

摘要： A semiconductor device having conductive bumps and a fabrication method thereof is proposed. The fabrication method includes the steps of forming a first metallic layer on a substrate having solder pads and a passivation layer formed thereon, and electrically connecting it to the solder pads; applying a second covering layer over exposed parts of the first metallic layer; subsequently, forming a second metallic layer on the second covering layer, and electrically connecting it to the exposed parts of the first metallic layer; applying a third covering layer, and forming openings for exposing parts of the second metallic layer to form thereon a conductive bump having a metallic standoff and a solder material. The covering layers and the metallic layers can provide a buffering effect for effectively absorbing the thermal stress imposed on the conductive bumps to prevent delamination caused by the UBM layers.

摘要翻译： 提出了具有导电凸块的半导体器件及其制造方法。 该制造方法包括以下步骤：在具有焊盘和形成在其上的钝化层的基板上形成第一金属层，并将其电连接到焊盘; 在第一金属层的暴露部分上施加第二覆盖层; 随后在第二覆盖层上形成第二金属层，并将其电连接到第一金属层的暴露部分; 施加第三覆盖层，以及形成用于暴露第二金属层的部分的开口以在其上形成具有金属支座和焊料材料的导电凸块。 覆盖层和金属层可以提供缓冲效果，用于有效地吸收施加在导电凸块上的热应力，以防止由UBM层引起的分层。

公开(公告)号：US20090261476A1

公开(公告)日：2009-10-22

申请号：US12148319

申请日：2008-04-18

申请人： Chien-Ping Huang ,  Chin-Huang Chang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao ,  Chun-Chi Ke

发明人： Chien-Ping Huang ,  Chin-Huang Chang ,  Chih-Ming Huang ,  Cheng-Hsu Hsiao ,  Chun-Chi Ke

IPC分类号： H01L23/482 ,  H01L21/60

CPC分类号： H01L24/19 ,  H01L21/6835 ,  H01L23/3114 ,  H01L24/24 ,  H01L24/82 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/24226 ,  H01L2224/82001 ,  H01L2225/1035 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311

摘要： A semiconductor device and a manufacturing method thereof are disclosed. The method includes the steps of providing a carrier board having conductive circuits disposed thereon and a plurality of chips with active surfaces having solder pads disposed thereon, wherein conductive bumps are disposed on the solder pads; mounting chips on the carrier board; filling the spacing between the chips with a dielectric layer and forming openings in the dielectric layer at periphery of each chip to expose the conductive circuits; forming a metal layer in the openings of the dielectric layer and at periphery of the active surface of the chips for electrically connecting the conductive bumps and the conductive circuits; and cutting along the dielectric layer between the chips and removing the carrier board to separate each chip and exposing the conductive circuits from the non-active surface.

摘要翻译： 公开了一种半导体器件及其制造方法。 该方法包括以下步骤：提供具有布置在其上的导电电路的载体板和具有设置在其上的焊料焊盘的有源表面的多个芯片，其中导电凸块设置在焊盘上; 将芯片安装在载板上; 用电介质层填充芯片之间的间隔，并在每个芯片周边的电介质层中形成开口以露出导电电路; 在所述电介质层的开口部和所述芯片的有源面的外围形成金属层，用于电连接所述导电凸块和所述导电电路; 并沿着芯片之间​​的电介质层切割并去除载体板以分离每个芯片并使导电电路与非活性表面相接触。

公开(公告)号：US20080169562A1

公开(公告)日：2008-07-17

申请号：US12005764

申请日：2007-12-27

申请人： Chun-Chi Ke ,  Chien-Ping Huang

发明人： Chun-Chi Ke ,  Chien-Ping Huang

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/14104 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013

摘要： A semiconductor device having conductive bumps and a fabrication method thereof are provided. The fabrication method mainly including steps of: providing a semiconductor substrate having a solder pad and a passivation layer formed thereon with a portion of the solder pads exposed from the passivation layer; disposing a first metal layer on the solder pad and a portion of the passivation layer around the solder pad; disposing a covering layer on the first metal layer and the passivation layer, and forming an aperture in the covering layer to expose a portion of the first metal layer, wherein a center of the aperture is deviated from that of the solder pad; deposing a metal pillar on the portion of the first metal layer; and deposing a solder material on an outer surface of the metal pillar for providing a better buffering effect.

摘要翻译： 提供了具有导电凸块的半导体器件及其制造方法。 该制造方法主要包括以下步骤：提供具有焊料焊盘和形成在其上的钝化层的半导体衬底，其中一部分焊料焊盘从钝化层暴露出来; 在焊料焊盘上设置第一金属层和围绕焊盘的钝化层的一部分; 在所述第一金属层和所述钝化层上设置覆盖层，以及在所述覆盖层中形成孔以暴露所述第一金属层的一部分，其中所述孔的中心偏离所述焊盘的中心; 在所述第一金属层的所述部分上沉积金属柱; 并在金属柱的外表面上沉积焊料，以提供更好的缓冲效果。

公开(公告)号：US20060258137A1

公开(公告)日：2006-11-16

申请号：US11226707

申请日：2005-09-13

申请人： Chun-Chi Ke ,  Kook-Jui Tai ,  Chien-Ping Huang

发明人： Chun-Chi Ke ,  Kook-Jui Tai ,  Chien-Ping Huang

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/14104 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/013

摘要： A semiconductor device and a fabrication method thereof ate provided. A semiconductor substrate having a plurality of bonding pads is prepared, and a first passivation layer, a second passivation layer and a metallic layer are successively formed on the semiconductor substrate. A third passivation layer is further applied on the semiconductor substrate and has a plurality of openings for exposing a portion of the metallic layer, wherein each of the openings is shifted in position from a corresponding one of the bonding pads by a distance not exceeding a radius of the bonding pad. A plurality of solder bumps are bonded to the exposed portion of the metallic layer and have a larger contact area with the third passivation layer. This provides better buffer to reduce stress exerted on the solder bumps, thereby preventing problems of cracking and delamination as in the prior art.

摘要翻译： 提供了半导体器件及其制造方法。 制备具有多个接合焊盘的半导体衬底，并且在半导体衬底上依次形成第一钝化层，第二钝化层和金属层。 第三钝化层进一步施加在半导体衬底上并且具有用于暴露金属层的一部分的多个开口，其中每个开口从对应的一个焊盘移位一定距离不超过半径 的焊盘。 多个焊料凸点与金属层的露出部分接合，并且与第三钝化层具有较大的接触面积。 这提供了更好的缓冲器以减少施加在焊料凸块上的应力，从而防止了现有技术中的开裂和分层问题。

公开(公告)号：US06258705B1

公开(公告)日：2001-07-10

申请号：US09642319

申请日：2000-08-21

申请人： Feng-Lung Chien ,  Randy H.Y. Lo ,  Chun-chi Ke

发明人： Feng-Lung Chien ,  Randy H.Y. Lo ,  Chun-chi Ke

IPC分类号： H01L2144

CPC分类号： H01L24/11 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/013

摘要： A method is proposed for forming circuit probing (CP) contact points on fine pitch peripheral bond pads (PBP) on a flip chip for the purpose of facilitating peripheral circuit probing of the internal circuitry of the flip chip. The proposed method is characterized in the forming of a dual-layer NiV/Cu metallization structure, rather than a triple-layer Al/NiV/Cu metallization structure, over each aluminum-based PBP, which includes a bottom layer of nickel-vanadium (NiV) deposited over the aluminum-based PBP and an upper layer of copper (Cu) deposited over the nickel-vanadium layer. When low-resolution photolithographic and etching equipment is used for photoresist mask definition for selective removal of the NiV/Cu metallization structure, the resulted photoresist masking can be misaligned to the PBP. However, since no aluminum layer is included in the metallization structure, a Cu/NiV specific etchant would only etch away the copper layer and the nickel-vanadium layer but not the aluminum-based PBP, thus leaving the unmasked portion of the aluminum-based PBP intact.

摘要翻译： 提出了一种用于在倒装芯片上的细间距外围接合焊盘（PBP）上形成电路探测（CP）接触点的方法，其目的在于便于倒装芯片的内部电路的外围电路探测。 所提出的方法的特征在于在每个基于铝的PBP上形成双层NiV / Cu金属化结构而不是三层Al / NiV / Cu金属化结构，其包括镍 - 钒的底层（ NiV）沉积在铝基PBP上并沉积在镍 - 钒层上的铜（Cu）上层。 当低分辨率光刻和蚀刻设备用于光刻胶掩模定义以选择性去除NiV / Cu金属化结构时，所得到的光刻胶掩模可能不对准PBP。 然而，由于在金属化结构中不包括铝层，所以Cu / NiV特定蚀刻剂将仅蚀刻掉铜层和镍 - 钒层而不是铝基PBP，从而留下铝基的未掩模部分 PBP完好无损。