公开(公告)号：US07773386B2

公开(公告)日：2010-08-10

申请号：US11976848

申请日：2007-10-29

Applicant: Yoshihisa Yamashita ,  Toshio Fujii ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Satoru Tomekawa ,  Hiroki Yabe

Inventor： Yoshihisa Yamashita ,  Toshio Fujii ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Satoru Tomekawa ,  Hiroki Yabe

IPC: H05K1/00

CPC classification number: H05K3/386 ,  H01L51/424 ,  H01L2924/0002 ,  H05K1/16 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4614 ,  H05K2201/0191 ,  H05K2201/0376 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A flexible substrate includes: (i) a film; (ii) an insulating resin layer formed on each of a front face of the film and a rear face of the film, which rear face is opposite to the front face; (iii) a front-sided wiring pattern embedded in the insulating resin layer formed on the front face of the film, and a rear-sided wiring pattern embedded in the insulating resin layer formed on the rear face of the film; and (iv) a via which is located between the front-sided wiring pattern and the rear-sided wiring pattern and serves to electrically interconnect the front-sided wiring pattern and the rear-sided wiring pattern, wherein the insulating resin layer formed on each of the front face and the rear face of the film is thicker than the film.

Abstract translation: 柔性基板包括：（i）膜; （ii）形成在所述膜的前表面和所述膜的后表面中的每一个上的绝缘树脂层，所述后表面与所述前表面相对; （iii）嵌入到形成在所述膜前表面上的所述绝缘树脂层中的正面布线图案和嵌入在所述膜背面形成的所述绝缘树脂层中的背面布线图案; 以及（iv）位于前侧布线图案和背面布线图案之间的通孔，用于将前侧布线图案和背面布线图案电连接，其中形成在每个布线图案上的绝缘树脂层 的膜的前表面和后表面比膜厚。

公开(公告)号：US07748110B2

公开(公告)日：2010-07-06

申请号：US11826758

申请日：2007-07-18

Applicant: Toshiyuki Asahi ,  Seiji Karashima ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Tousaku Nishiyama ,  Koichi Hirano ,  Osamu Shibata ,  Takeshi Nakayama ,  Yoshiyuki Saito

Inventor： Toshiyuki Asahi ,  Seiji Karashima ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Tousaku Nishiyama ,  Koichi Hirano ,  Osamu Shibata ,  Takeshi Nakayama ,  Yoshiyuki Saito

IPC: H05K3/36

CPC classification number: H05K3/403 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H01R13/2414 ,  H05K1/0218 ,  H05K1/0284 ,  H05K1/141 ,  H05K1/145 ,  H05K1/182 ,  H05K3/20 ,  H05K3/3442 ,  H05K3/361 ,  H05K3/366 ,  H05K3/368 ,  H05K2201/043 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/055 ,  H05K2201/056 ,  H05K2201/09036 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2203/302 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49208 ,  H01L2924/00

Abstract: A connection member can be produced without a via-forming step. The connection member includes an insulating substrate which has an upper surface, a lower surface opposed to the upper surface, and a side surface which connects these surfaces; and at least one wiring which extends from the upper surface to the lower surface through the side surface.

Abstract translation: 可以在没有通孔形成步骤的情况下制造连接构件。 连接构件包括绝缘基板，其具有上表面，与上表面相对的下表面和连接这些表面的侧表面; 以及至少一个通过侧面从上表面延伸到下表面的布线。

公开(公告)号：US20090023245A1

公开(公告)日：2009-01-22

申请号：US11910810

申请日：2006-03-16

Applicant: Takashi Kitae ,  Seiichi Nakatani ,  Seiji Karashima ,  Yoshihisa Yamashita ,  Takashi Ichiryu

Inventor： Takashi Kitae ,  Seiichi Nakatani ,  Seiji Karashima ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC: H01L21/00

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11001 ,  H01L2224/11003 ,  H01L2224/1141 ,  H01L2224/11502 ,  H01L2224/11522 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/165 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/29299 ,  H01L2224/29305 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29313 ,  H01L2224/29316 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2224/832 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/8388 ,  H01L2224/83885 ,  H01L2224/83886 ,  H01L2224/83887 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1579 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/0264 ,  H05K2203/087 ,  H05K2203/1178 ,  Y02P70/613 ,  H01L2924/01031 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/066 ,  H01L2924/06 ,  H01L2924/0675 ,  H01L2924/0695 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: The invention involves mounting a solder resin composition (6) including a solder powder (5a) and a resin (4) on the first electronic component (2); arranging such that the connecting terminals (3) of the first electronic component (2) and the electrode terminals (7) of the second electronic component (8) are facing each other; ejecting a gas (9a) from a gas generation source (1) included in the first electronic component (2) by heating the first electronic component (2) and the solder resin composition; and inducing the flow of the solder powder (5a) in the solder resin composition (6) by inducing convection of the gas (9a) in the solder resin composition (6), and electrically connecting the connecting terminals (3) and the electrode terminals (7) by self-assembly on the connecting terminals (3) and the electrode terminals (7). Through this are provided a flip chip packaging method that enables connecting, with high connection reliability, electrode terminals of a semiconductor chip wired with narrow pitch and connecting terminals of a circuit board, and a bump formation method for packaging on a circuit board.

Abstract translation: 本发明涉及将包含焊料粉末（5a）和树脂（4）的焊料树脂组合物（6）安装在第一电子部件（2）上; 排列成使得第一电子部件（2）的连接端子（3）和第二电子部件（8）的电极端子（7）彼此面对; 通过加热第一电子部件（2）和焊料树脂组合物，从包括在第一电子部件（2）中的气体发生源（1）喷出气体（9a） 并且通过引起焊料树脂组合物（6）中的气体（9a）的对流而引起焊料粉末（5a）在焊料树脂组合物（6）中的流动，并将连接端子（3）和电极端子 （7）通过在连接端子（3）和电极端子（7）上的自组装。 通过这种方式提供了一种倒装芯片封装方法，其以高连接可靠性连接具有窄间距的半导体芯片的电极端子和电路板的连接端子，以及用于封装在电路板上的凸块形成方法。

公开(公告)号：US20070243664A1

公开(公告)日：2007-10-18

申请号：US11579299

申请日：2006-03-07

Applicant: Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Yoshihiro Tomita ,  Seiichi Nakatani

Inventor： Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Yoshihiro Tomita ,  Seiichi Nakatani

IPC: H05K3/34 ,  H01L21/00 ,  H01L21/44 ,  H05K3/00

CPC classification number: H01L21/563 ,  B23K35/0244 ,  H01L21/67144 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1131 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/133 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2224/83886 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/30105 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/1361 ,  Y02P70/613 ,  Y10T29/53178 ,  H01L2224/05599

Abstract: [Problem] To provide a flip-chip mounting method and a bump formation method applicable to flip-chip mounting of a next generation LSI and having high productivity and high reliability. [Means for Solving Problem] A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are dipped in a dipping bath 40 containing a melted resin 14 including melted solder particles for a given period of time. In this dipping process, the melted solder particles self-assemble between the connection terminals 11 of the circuit board 21 and the electrode terminals 12 of the semiconductor chip 20, so as to form connectors 22 between these terminals. Thereafter, the semiconductor chip 20 and the circuit board 21 are taken out of the dipping bath 40, and the melted resin 14 having permeated into the gap between the semiconductor chip 20 and the circuit board 21 is cured, so as to complete a flip-chip mounting body.

Abstract translation: [问题]提供一种适用于下一代LSI的倒装安装并具有高生产率和高可靠性的倒装芯片安装方法和凸块形成方法。 解决问题的手段具有多个电极端子12的半导体芯片20被保持为具有多个连接端子11的电路板21，其间设置有给定的间隙，并且半导体芯片20和电路板21 将该状态浸渍在包含熔融的焊料颗粒的熔融树脂14的浸渍浴40中一段给定的时间。 在该浸渍过程中，熔融的焊料颗粒自组装在电路板21的连接端子11和半导体芯片20的电极端子12之间，从而在这些端子之间形成连接器22。 此后，半导体芯片20和电路板21从浸渍浴40中取出，并且已经渗透到半导体芯片20和电路板21之间的间隙中的熔融树脂14固化， 芯片安装体。

公开(公告)号：US20070224735A1

公开(公告)日：2007-09-27

申请号：US11750617

申请日：2007-05-18

Applicant: Seiji Karashima ,  Seiichi Nakatani ,  Yasuhiro Sugaya ,  Toshiyuki Asahi ,  Takashi Ichiryu

Inventor： Seiji Karashima ,  Seiichi Nakatani ,  Yasuhiro Sugaya ,  Toshiyuki Asahi ,  Takashi Ichiryu

IPC: H01L21/82

CPC classification number: G02B6/4249 ,  G02B6/3608 ,  G02B6/3636 ,  G02B6/3668 ,  G02B6/3676 ,  G02B6/3692 ,  G02B6/4214 ,  H05K1/0274 ,  H05K2203/167

Abstract: A fabrication method for an optical transmission channel board includes a first step of forming on a substrate a layer containing an electrically conductive material, and a second step of patterning said layer containing an electrically conductive material formed on said substrate, and thereby forming circuit patterns at least a part of which is used as an electric circuit and at least a part of which positionally regulates an optical transmission channel.

Abstract translation: 用于光传输通道板的制造方法包括在衬底上形成含有导电材料的层的第一步骤，以及第二步骤，使包含形成在所述衬底上的导电材料的层的图案化，从而形成电路图案 其中至少一部分用作电路，其中至少一部分位置地调节光传输通道。

公开(公告)号：US07242823B2

公开(公告)日：2007-07-10

申请号：US11041101

申请日：2005-01-21

Applicant: Seiji Karashima ,  Seiichi Nakatani ,  Yasuhiro Sugaya ,  Toshiyuki Asahi ,  Takashi Ichiryu

Inventor： Seiji Karashima ,  Seiichi Nakatani ,  Yasuhiro Sugaya ,  Toshiyuki Asahi ,  Takashi Ichiryu

IPC: G02B6/12 ,  H01L29/00

CPC classification number: G02B6/4249 ,  G02B6/3608 ,  G02B6/3636 ,  G02B6/3668 ,  G02B6/3676 ,  G02B6/3692 ,  G02B6/4214 ,  H05K1/0274 ,  H05K2203/167

Abstract: An optical transmission board is provided. The optical transmission board includes an optical transmission channel, a retention board for retaining the optical transmission channel and circuit patterns. The circuit patterns are formed on the retention board and a part of the circuit patterns is used as an electric circuit. The optical transmission channel is positionally regulated by the part of the circuit patterns.

Abstract translation: 提供一种光传输板。 光传输板包括光传输通道，用于保持光传输通道和电路图案的保持板。 电路图案形成在保持板上，一部分电路图形用作电路。 光传输通道由电路图案的一部分位置调节。

公开(公告)号：US07205483B2

公开(公告)日：2007-04-17

申请号：US11079371

申请日：2005-03-15

Applicant: Yoshihisa Yamashita ,  Hiroki Yabe ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Satoru Tomekawa ,  Toshio Fujii ,  Seiji Karashima

Inventor： Yoshihisa Yamashita ,  Hiroki Yabe ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Satoru Tomekawa ,  Toshio Fujii ,  Seiji Karashima

IPC: H05K1/11

CPC classification number: H05K3/4084 ,  G03G15/225 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K1/0393 ,  H05K3/102 ,  H05K3/1266 ,  H05K3/20 ,  H05K3/207 ,  H05K3/386 ,  H05K3/4652 ,  H05K2201/0376 ,  H05K2203/0143 ,  H05K2203/0195 ,  H05K2203/0517 ,  H05K2203/1189 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A flexible substrate comprises a film, a first insulating resin layer on a front face of the film, a second insulating resin layer on a rear face of the film, a front-sided wiring pattern embedded in the first insulating resin layer, and a rear-sided wiring pattern embedded in the second insulating resin layer. A surface of the front-sided wiring pattern is flush with a surface of the first insulating resin layer, and a surface of the rear-sided wiring pattern is flush with a surface of the second insulating resin layer. A part of at least one of the front-sided wiring pattern and the rear-sided wiring pattern is dented toward a part of the other of the at least one of the front-sided wiring pattern and the rear-sided wiring pattern such that a portion of the front-sided wiring pattern and a portion of the rear-sided wiring pattern are jointed to each other to form a junction.

Abstract translation: 柔性基板包括膜，膜的正面上的第一绝缘树脂层，膜背面的第二绝缘树脂层，嵌入第一绝缘树脂层中的前侧布线图案，以及后部 嵌入在第二绝缘树脂层中的布线图案。 前侧布线图案的表面与第一绝缘树脂层的表面齐平，并且背面布线图案的表面与第二绝缘树脂层的表面齐平。 前侧布线图案和背面布线图案中的至少一个的一部分朝向前侧布线图案和背面布线图案中的至少一个中的另一个的一部分凹陷，使得 前侧布线图案的一部分和背面布线图案的一部分彼此接合以形成结。

公开(公告)号：US20050168960A1

公开(公告)日：2005-08-04

申请号：US11043123

申请日：2005-01-27

Applicant: Toshiyuki Asahi ,  Seiji Karashima ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Tousaku Nishiyama

Inventor： Toshiyuki Asahi ,  Seiji Karashima ,  Takashi Ichiryu ,  Seiichi Nakatani ,  Tousaku Nishiyama

IPC: H01L21/68 ,  H01L21/98 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H05K1/00 ,  H05K1/18 ,  H05K3/20 ,  H05K3/40

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L23/49805 ,  H01L23/5389 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0284 ,  H05K1/183 ,  H05K1/187 ,  H05K3/20 ,  H05K3/403 ,  H05K2203/302 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A module with a built-in component is provided which can be produced without a via-forming step. The module with a built-in component 100 includes an insulating sheet substrate 10 which has an upper surface 10a, a lower surface 10b opposed to the upper surface 10b and a side surface 10c which connects these surfaces; at least one wiring 20 which extends from the upper surface to the lower surface through the side surface; and an electronic component 32 which is disposed within the sheet substrate.

Abstract translation: 提供具有内置部件的模块，其可以在没有通孔形成步骤的情况下制造。 具有内置部件100的模块包括绝缘片基板10，其具有上表面10a，与上表面10b相对的下表面10b和连接这些表面的侧表面10c; 至少一个布线20，其通过侧表面从上表面延伸到下表面; 以及设置在片状基板内的电子部件32。

公开(公告)号：US08691683B2

公开(公告)日：2014-04-08

申请号：US13046151

申请日：2011-03-11

Applicant: Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Yoshihiro Tomita ,  Seiichi Nakatani

Inventor： Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Yoshihiro Tomita ,  Seiichi Nakatani

IPC: H01L21/56

CPC classification number: H01L21/563 ,  B23K35/0244 ,  H01L21/67144 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1131 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/133 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2224/83886 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/30105 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/1361 ,  Y02P70/613 ,  Y10T29/53178 ,  H01L2224/05599

Abstract: [Means for Solving Problem] A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are dipped in a dipping bath 40 containing a melted resin 14 including melted solder particles for a given period of time. In this dipping process, the melted solder particles self-assemble between the connection terminals 11 of the circuit board 21 and the electrode terminals 12 of the semiconductor chip 20, so as to form connectors 22 between these terminals. Thereafter, the semiconductor chip 20 and the circuit board 21 are taken out of the dipping bath 40, and the melted resin 14 having permeated into the gap between the semiconductor chip 20 and the circuit board 21 is cured, so as to complete a flip-chip mounting body.

Abstract translation: 解决问题的手段具有多个电极端子12的半导体芯片20被保持为具有多个连接端子11的电路板21，其间设置有给定的间隙，半导体芯片20和电路板21 将该状态浸渍在包含熔融的焊料颗粒的熔融树脂14的浸渍浴40中一段给定的时间。 在该浸渍过程中，熔融的焊料颗粒自组装在电路板21的连接端子11和半导体芯片20的电极端子12之间，从而在这些端子之间形成连接器22。 此后，半导体芯片20和电路板21从浸渍浴40中取出，并且已经渗透到半导体芯片20和电路板21之间的间隙中的熔融树脂14固化， 芯片安装体。

公开(公告)号：US08367488B2

公开(公告)日：2013-02-05

申请号：US13054049

申请日：2010-02-05

Applicant: Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano

Inventor： Takashi Ichiryu ,  Seiichi Nakatani ,  Koichi Hirano

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/78603 ,  H01L27/1218 ,  H01L27/1266 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/78681 ,  H01L29/7869 ,  H01L2224/24195 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/92244 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: A method includes the steps of preparing a multilayer film 80 formed by sequentially stacking a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40; forming a source electrode 42s and a drain electrode 42d comprised of the second metal layer 40 by etching the second metal layer 40; pressure-bonding a resin layer 50 onto a surface of the multilayer film 80 provided with the source electrode 42s and the drain electrode 42d to burry the source electrode 42s and the drain electrode 42d in the resin layer 50; and forming a gate electrode 10g comprised of the first metal layer 10 by etching the first metal layer 10. The inorganic insulating layer 20g functions as a gate insulating film. The semiconductor layer 30 functions as a channel.

Abstract translation: 一种方法包括制备通过顺序堆叠第一金属层10，无机绝缘层20，半导体层30和第二金属层40而形成的多层膜80的步骤; 通过蚀刻第二金属层40形成由第二金属层40构成的源电极42s和漏电极42d; 将树脂层50压接到设置有源电极42s和漏电极42d的多层膜80的表面，以将树脂层50中的源电极42s和漏电极42d嵌入; 以及通过蚀刻第一金属层10形成由第一金属层10构成的栅极电极10g。无机绝缘层20g用作栅极绝缘膜。 半导体层30用作沟道。