公开(公告)号：US09536829B2

公开(公告)日：2017-01-03

申请号：US14483258

申请日：2014-09-11

Applicant: International Business Machines Corporation

Inventor： Mukta G. Farooq ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/58 ,  H01L23/525 ,  H01L23/48

CPC classification number: H01L23/5256 ,  H01L23/481 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An method including forming a back end of the line (BEOL) wiring portion directly on top of a semiconductor base portion, the BEOL wiring portion including a plurality of layers of a metallic material and a dielectric material and excluding a semiconductor material, forming a through-substrate via through the BEOL wiring portion and the semiconductor base portion, forming an electronic fuse in the BEOL wiring portion adjacent to the through-substrate via, and forming a guard ring in the BEOL wiring portion surrounding the through-substrate via and the electronic fuse in the BEOL wiring portion, the through-substrate via in the semiconductor base portion being free from the guard ring.

Abstract translation: 一种包括在半导体基部的顶部直接形成线（BEOL）布线部分的后端的方法，所述BEOL布线部分包括多层金属材料和电介质材料，并且不包括半导体材料，形成通孔 - 通过BEOL布线部分和半导体基底部衬底通孔，在与穿通基板通孔相邻的BEOL布线部分中形成电子熔断器，并且在围绕贯穿基板通孔的BEOL布线部分中形成保护环，并且电子 在BEOL布线部分中熔断，半导体基底部分中的贯通基板通孔没有保护环。

公开(公告)号：US09515035B2

公开(公告)日：2016-12-06

申请号：US14577230

申请日：2014-12-19

Applicant: International Business Machines Corporation

Inventor： Timothy D. Sullivan ,  Thomas A. Wassick

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L23/49838 ,  G06F17/5077 ,  H01L21/76898 ,  H01L22/14 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/647 ,  H01L24/10 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/1413 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Wiring structures, methods for providing a wiring structure, and methods for distributing currents with a wiring structure from one or more through-substrate vias to multiple bumps. A first current is directed from a first through-substrate via of a first electrical resistance through a first connection line to a first bump and directing a second current from the first through-substrate via through a second connection line of a second electrical resistance to a second bump. The first connection line has a first length relative to a first position of the first bump and a first cross-sectional area, the second connection line has a second length relative to a first position of the second bump and a second cross-sectional area, the second length is different from the first length, and the second cross-sectional area is different from the first cross-sectional area.

Abstract translation: 布线结构，用于提供布线结构的方法以及用布线结构从一个或多个贯穿基板通孔分配到多个凸起的方法。 第一电流从第一通过基板通过第一电阻通过第一连接线引导到第一凸起并且引导来自第一穿通基板的第二电流通过第二电阻的第二连接线到 第二次碰撞 第一连接线具有相对于第一凸块的第一位置的第一长度和第一横截面积，第二连接线相对于第二凸块的第一位置具有第二长度和第二横截面积， 第二长度与第一长度不同，第二横截面积与第一横截面积不同。

公开(公告)号：US20160079166A1

公开(公告)日：2016-03-17

申请号：US14483258

申请日：2014-09-11

Applicant: International Business Machines Corporation

Inventor： Mukta G. Farooq ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/525 ,  H01L21/3205 ,  H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L23/58

CPC classification number: H01L23/5256 ,  H01L23/481 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An method including forming a back end of the line (BEOL) wiring portion directly on top of a semiconductor base portion, the BEOL wiring portion including a plurality of layers of a metallic material and a dielectric material and excluding a semiconductor material, forming a through-substrate via through the BEOL wiring portion and the semiconductor base portion, forming an electronic fuse in the BEOL wiring portion adjacent to the through-substrate via, and forming a guard ring in the BEOL wiring portion surrounding the through-substrate via and the electronic fuse in the BEOL wiring portion, the through-substrate via in the semiconductor base portion being free from the guard ring.

Abstract translation: 一种包括在半导体基部的顶部直接形成线（BEOL）布线部分的后端的方法，所述BEOL布线部分包括多层金属材料和电介质材料，并且不包括半导体材料，形成通孔 - 通过BEOL布线部分和半导体基底部衬底通孔，在与穿通基板通孔相邻的BEOL布线部分中形成电子熔断器，并且在围绕贯穿基板通孔的BEOL布线部分中形成保护环，并且电子 在BEOL布线部分中熔断，半导体基底部分中的贯通基板通孔没有保护环。

公开(公告)号：US09275868B2

公开(公告)日：2016-03-01

申请号：US13946456

申请日：2013-07-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shawn A. Adderly ,  Jeffrey P. Gambino ,  Max L. Lifson ,  Matthew D. Moon ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas

IPC: H01L21/308 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L21/30604 ,  H01L21/3065 ,  H01L21/3083

Abstract: Substrates (wafers) with uniform backside roughness and methods of manufacture are disclosed. The method includes forming a material on a backside of a wafer. The method further includes patterning the material to expose portions of the backside of the wafer. The method further includes roughening the backside of the wafer through the patterned material to form a uniform roughness.

Abstract translation: 公开了具有均匀背面粗糙度的基板（晶片）和制造方法。 该方法包括在晶片的背面形成材料。 该方法还包括图案化材料以暴露晶片背面的部分。 该方法还包括通过图案化材料粗糙化晶片的背面以形成均匀的粗糙度。

公开(公告)号：US09269683B2

公开(公告)日：2016-02-23

申请号：US14200613

申请日：2014-03-07

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/12 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/11 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13618 ,  H01L2224/1362 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.

Abstract translation: 公开了一种用改进的导电焊盘形成芯片的芯片和方法，其允许与芯片载体或另一个集成电路芯片的柔性C4连接。 垫具有三维几何形状（例如，金字塔或锥形），其具有与芯片表面相邻的基部，与基部相对的顶点以及可选地在顶点顶部的蘑菇形帽。 每个焊盘可以包括单层导电材料或多层导电材料（例如，堆叠在非润湿层上方的润湿层）。 焊盘可以被暴露以允许随后连接到芯片载体或第二芯片上的相应焊料凸块。 或者，焊球可以定位在导电焊盘上，以允许随后连接到芯片载体或第二芯片上相应的焊膏填充的开口。

公开(公告)号：US20150380326A1

公开(公告)日：2015-12-31

申请号：US14320598

申请日：2014-06-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Mukta G. Farooq ,  John A. Griesemer ,  Chandrasekaran Kothandaraman ,  John M. Safran ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L21/66 ,  G01R31/08 ,  H01L23/48

CPC classification number: G01R31/08 ,  G01R31/2856 ,  G01R31/2858 ,  H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure, such as a wafer, chip, IC, design structure, etc., includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV extends completely through a semiconductor chip and the EM monitor includes a plurality of EM wires proximately arranged about the TSV perimeter. An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV, measuring an electrical resistance drop across the EM monitor wiring, determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance, and/or determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

Abstract translation: 诸如晶片，芯片，IC，设计结构等的结构包括硅通孔（TSV）和电迁移（EM）监视器。 TSV完全延伸穿过半导体芯片，并且EM监测器包括围绕TSV周边近似排列的多个EM电线。 EM测试方法包括强制电流通过紧邻TSV周界布置的EM监测器接线，测量EM监测器接线两端的电阻降，确定在EM监测器接线和TSV之间是否存在电短路 测量的电阻，和/或确定由于TSV引起的接近效应，EM监测布线内是否存在早期电开路或电阻增加。

公开(公告)号：US09190375B2

公开(公告)日：2015-11-17

申请号：US14248373

申请日：2014-04-09

Applicant: International Business Machines Corporation

Inventor： Stephen P. Ayotte ,  Sebastien S. Quesnel ,  Glen E. Richard ,  Timothy D. Sullivan ,  Timothy M. Sullivan

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/02126 ,  H01L2224/0345 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/0516 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05686 ,  H01L2224/10156 ,  H01L2224/10175 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81222 ,  H01L2224/81815 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A method of applying inductive heating to join an integrated circuit chip to an electrical substrate using solder bumps including applying a magnetic field to a magnetic liner in thermal contact with a solder bump on the integrated circuit chip. The magnetic field causes Joule heating in the magnetic liner sufficient to melt the solder bump, which has a lower portion embedded in a first dielectric layer and an upper portion at least partially embedded in a second dielectric layer. The lower portion is in electrical contact with a conductive pad, the first dielectric layer is above the conductive pad and the second dielectric layer is on top of the first dielectric layer. The duration of application of the magnetic field is controlled to achieve a joining temperature that is approximately halfway between the storage and operating temperatures of the integrated circuit chip.

Abstract translation: 一种施加感应加热以将集成电路芯片连接到电气基板的方法，其使用焊料凸块，包括将磁场施加到与集成电路芯片上的焊料凸块热接触的磁性衬垫。 磁场使得磁性衬垫中的焦耳加热足以熔化焊料凸块，焊料凸块具有嵌入在第一电介质层中的下部和至少部分地嵌入第二介电层中的上部。 下部与导电焊盘电接触，第一介电层位于导电焊盘的上方，第二介电层位于第一介质层的顶部。 控制施加磁场的持续时间以实现大约在集成电路芯片的存储和工作温度之间的接合温度。

公开(公告)号：US09177931B2

公开(公告)日：2015-11-03

申请号：US14191857

申请日：2014-02-27

Applicant: International Business Machines Corporation

Inventor： Stephen P. Ayotte ,  Sebastien Quesnel ,  Glen E. Richard ,  Timothy D. Sullivan ,  Timothy M. Sullivan

IPC: H01L29/15 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/49827 ,  H01L23/53295 ,  H01L24/05 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/02123 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05095 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05551 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01074

Abstract: Embodiments of the present invention provide a semiconductor structure and method to reduce thermal energy transfer during chip-join processing. In certain embodiments, the semiconductor structure comprises a thermal insulating element formed under a first conductor. The semiconductor structure also comprises a solder bump formed over the first conductor. The semiconductor structure further comprises a second conductor formed on a side of the thermal insulating element and in electrical communication with the first conductor and a third conductor. The third conductor is formed to be in thermal or electrical communication with the thermal insulating element. The thermal insulating element includes thermal insulating material and the thermal insulating element is structured to reduce thermal energy transfer during a chip-join process from the solder bump to a metal level included in the semiconductor structure.

Abstract translation: 本发明的实施例提供了一种在芯片连接处理期间减少热能传递的半导体结构和方法。 在某些实施例中，半导体结构包括形成在第一导体下的绝热元件。 半导体结构还包括形成在第一导体上的焊料凸块。 半导体结构还包括形成在绝热元件的一侧并与第一导体和第三导体电连通的第二导体。 第三导体形成为与隔热元件热连接或电连通。 绝热元件包括绝热材料，并且隔热元件被构造为减少从焊料凸块到包括在半导体结构中的金属水平的芯片接合过程期间的热能传递。

公开(公告)号：US20150243618A1

公开(公告)日：2015-08-27

申请号：US14191857

申请日：2014-02-27

Applicant: International Business Machines Corporation

Inventor： Stephen P. Ayotte ,  Sebastien Quesnel ,  Glen E. Richard ,  Timothy D. Sullivan ,  Timothy M. Sullivan

IPC: H01L23/00 ,  H01L23/373 ,  H01L23/367

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/49827 ,  H01L23/53295 ,  H01L24/05 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/02123 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05095 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05551 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01074

Abstract: Embodiments of the present invention provide a semiconductor structure and method to reduce thermal energy transfer during chip-join processing. In certain embodiments, the semiconductor structure comprises a thermal insulating element formed under a first conductor. The semiconductor structure also comprises a solder bump formed over the first conductor. The semiconductor structure further comprises a second conductor formed on a side of the thermal insulating element and in electrical communication with the first conductor and a third conductor. The third conductor is formed to be in thermal or electrical communication with the thermal insulating element. The thermal insulating element includes thermal insulating material and the thermal insulating element is structured to reduce thermal energy transfer during a chip-join process from the solder bump to a metal level included in the semiconductor structure.

Abstract translation: 本发明的实施例提供了一种在芯片连接处理期间减少热能传递的半导体结构和方法。 在某些实施例中，半导体结构包括形成在第一导体下的绝热元件。 半导体结构还包括形成在第一导体上的焊料凸块。 半导体结构还包括形成在绝热元件的一侧并与第一导体和第三导体电连通的第二导体。 第三导体形成为与隔热元件热连接或电连通。 绝热元件包括绝热材料，并且隔热元件被构造为减少从焊料凸块到包括在半导体结构中的金属水平的芯片接合过程期间的热能传递。

公开(公告)号：US09059106B2

公开(公告)日：2015-06-16

申请号：US13664812

申请日：2012-10-31

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L23/3114 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0236 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05575 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/06102 ,  H01L2224/11848 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/1531 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Structures and methods of making a flip chip package that employ polyimide pads of varying heights at a radial distance from a center of an integrated circuit (IC) chip for a flip chip package. The polyimide pads may be formed under electrical connectors, which connect the IC chip to a chip carrier of the flip chip package, so that electrical connectors formed on polyimide pads of greater height are disposed at a greater radial distance from the center of the IC chip, while electrical connectors formed on polyimide pads of a lesser height are disposed more proximately to the center of the IC chip. Electrical connectors of a greater relative height to the IC chip's surface may compensate for a gap, produced by heat-induced warpage during the making of the flip chip package, that separates the electrical connectors on the IC chip from flip chip attaches on the chip carrier.