公开(公告)号：US08004085B2

公开(公告)日：2011-08-23

申请号：US12593824

申请日：2008-02-13

申请人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

发明人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/10 ,  H01L29/73 ,  H01L29/74

CPC分类号： H01L23/5283 ,  H01L23/3171 ,  H01L23/5286 ,  H01L24/14 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/01047 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

摘要： A semiconductor device has an element interconnection 2, a top-layer element interconnection 4, a super-connect interconnection 10 and a bump 7. The element interconnection 2 is provided on a semiconductor substrate 1 through a plurality of insulating layers 50. The top-layer element interconnection 4 is formed above the element interconnection 2 by using a substantially equivalent process equipment. The super-connect interconnection 10 is provided on the top-layer element interconnection 4 through a super-connect insulating layer 9 having a thickness five or more times larger than that of the insulating layer 5, and has a thickness three or more times larger than that of each the element interconnection 2 and the top-layer element interconnection 4. The bump 7 is formed on the super-connect interconnection 10. The top-layer element interconnection 4 has a signal pad 4s, a power source pad 4v and a ground pad 4g. An area of the signal pad 4s is smaller than each area of the power source pad 4v and the ground pad 4g.

摘要翻译： 半导体器件具有元件互连2，顶层元件互连4，超连接互连10和凸块7.元件互连2通过多个绝缘层50设置在半导体衬底1上。 层元件互连4通过使用基本相同的处理设备形成在元件互连2上方。 超连接互连10通过具有比绝缘层5的厚度大五倍以上的厚度的超连接绝缘层9设置在顶层元件布线4上，并且具有比绝缘层5的厚度大三倍以上的厚度 元件互连2和顶层元件互连4中的每一个。凸块7形成在超连接互连10上。顶层元件互连4具有信号焊盘4s，电源焊盘4v和接地 垫4g。 信号焊盘4s的面积比电源焊盘4v和接地焊盘4g的面积小。

公开(公告)号：US20110155433A1

公开(公告)日：2011-06-30

申请号：US13060990

申请日：2009-08-25

申请人： Takuo Funaya ,  Shintaro Yamamichi ,  Daisuke Ohshima ,  Yoshiki Nakashima

发明人： Takuo Funaya ,  Shintaro Yamamichi ,  Daisuke Ohshima ,  Yoshiki Nakashima

IPC分类号： H05K1/00 ,  H01K3/10

CPC分类号： H05K1/115 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/3511 ,  H05K1/0366 ,  H05K1/185 ,  H05K3/4069 ,  H05K3/421 ,  H05K3/424 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/09563 ,  H05K2201/09854 ,  H05K2201/2072 ,  Y10T29/49165 ,  H01L2924/00

摘要： A wiring board is configured by stacking one or more conductor wiring layers and one or more insulating resin layers and comprising one or more metal vias configured to penetrate the insulating resin layer, wherein the boundary surface between the metal via and the insulating resin layer has a concavo-convex boundary cross-section structure in which the metal via and the insulating resin layer are engaged with each other.

摘要翻译： 布线板通过层叠一个或多个导体布线层和一个或多个绝缘树脂层而构成，并且包括被配置为穿透绝缘树脂层的一个或多个金属通孔，其中金属孔和绝缘树脂层之间的边界面具有 金属通孔和绝缘树脂层彼此接合的凹凸边界横截面结构。

公开(公告)号：US07816782B2

公开(公告)日：2010-10-19

申请号：US11174526

申请日：2005-07-06

申请人： Hideya Murai ,  Tadanori Shimoto ,  Takuo Funaya ,  Katsumi Kikuchi ,  Shintaro Yamamichi ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata ,  Kouji Matsui ,  Shinichi Miyazaki

发明人： Hideya Murai ,  Tadanori Shimoto ,  Takuo Funaya ,  Katsumi Kikuchi ,  Shintaro Yamamichi ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata ,  Kouji Matsui ,  Shinichi Miyazaki

IPC分类号： H01L23/14 ,  H01L23/12

CPC分类号： H01L21/4857 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K3/007 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4614 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2203/0152 ,  H05K2203/061 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

摘要翻译： 用于安装半导体的布线基板设置有绝缘膜，形成在绝缘膜中的布线以及通过通孔电连接到导线的多个电极垫。 电极焊盘被设置为使其表面暴露于绝缘膜的前表面和后表面，并且电极焊盘的侧表面的至少一部分被埋在绝缘膜中。 绝缘膜通过在相应的两个金属板上形成电极焊盘而形成，然后在相应的金属板上层叠绝缘层和电线以覆盖电极焊盘，并将绝缘层彼此粘合在一起，然后除去 金属板。

公开(公告)号：US20100117228A1

公开(公告)日：2010-05-13

申请号：US12593824

申请日：2008-02-13

申请人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

发明人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L23/5283 ,  H01L23/3171 ,  H01L23/5286 ,  H01L24/14 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/01047 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

摘要： A semiconductor device has an element interconnection 2, a top-layer element interconnection 4, a super-connect interconnection 10 and a bump 7. The element interconnection 2 is provided on a semiconductor substrate 1 through a plurality of insulating layers 50. The top-layer element interconnection 4 is formed above the element interconnection 2 by using a substantially equivalent process equipment. The super-connect interconnection 10 is provided on the top-layer element interconnection 4 through a super-connect insulating layer 9 having a thickness five or more times larger than that of the insulating layer 5, and has a thickness three or more times larger than that of each the element interconnection 2 and the top-layer element interconnection 4. The bump 7 is formed on the super-connect interconnection 10. The top-layer element interconnection 4 has a signal pad 4s, a power source pad 4v and a ground pad 4g. An area of the signal pad 4s is smaller than each area of the power source pad 4v and the ground pad 4g.

摘要翻译： 半导体器件具有元件互连2，顶层元件互连4，超连接互连10和凸块7.元件互连2通过多个绝缘层50设置在半导体衬底1上。 层元件互连4通过使用基本相同的处理设备形成在元件互连2上方。 超连接互连10通过具有比绝缘层5的厚度大五倍以上的厚度的超连接绝缘层9设置在顶层元件布线4上，并且具有比绝缘层5的厚度大三倍以上的厚度 元件互连2和顶层元件互连4中的每一个。凸块7形成在超连接互连10上。顶层元件互连4具有信号焊盘4s，电源焊盘4v和接地 垫4g。 信号焊盘4s的面积比电源焊盘4v和接地焊盘4g的面积小。

公开(公告)号：US20100044845A1

公开(公告)日：2010-02-25

申请号：US12298737

申请日：2007-04-27

申请人： Takuo Funaya ,  Shintaro Yamamichi

发明人： Takuo Funaya ,  Shintaro Yamamichi

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L21/50 ,  H01L21/768

CPC分类号： H05K1/185 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/2402 ,  H01L2224/24051 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3511 ,  H05K3/20 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0376 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10969 ,  H05K2203/061 ,  H01L2924/00

摘要： [Problem to be Solved] There are provided a circuit substrate, an electronic device arrangement and a manufacturing process for the circuit substrate which enable to directly implement the surface mounting and so on of electronic components on the conductive wiring without forming solder resist, and also which enable to enhance high speed transmission characteristics and to enlarge wiring rule for the electrode terminal of the function element to be contained therein, and to implement with excellent workability and reliability when connecting the electronic device.[Solution] A circuit substrate comprising a function element 1 with an electrode terminal 5 a base member containing the function element 1 therein and having at least one layer of a conductive wiring formed on its front side face and rear side face respectively, and a via 6 connecting the electrode terminal 5 with the conductive wiring 3 formed on the base member, wherein the conductive wiring formed on either one of the front side face and the rear side face of the base member is arranged such that a surface exposed outside from the base member is in the same plane with or inside a surface of the base member on which the conductive wiring is formed.

摘要翻译： [待解决的问题]提供了一种用于电路基板的电路基板，电子器件布置和制造工艺，其能够直接实现导电布线上的电子部件的表面安装等而不形成阻焊剂，并且还 能够提高高速传输特性，并且扩大要包含在其中的功能元件的电极端子的布线规则，并且在连接电子设备时实现优异的可加工性和可靠性。 [解决方案]一种电路基板，包括具有电极端子5的功能元件1，分别在其前侧面和后侧面上形成有至少一层导电布线的基座部件，其中包括功能元件1，以及通孔 6，其将电极端子5与形成在基底构件上的导电布线3连接，其中形成在基底构件的前侧面和后侧面中的任一个上的导电布线布置成使得从底部暴露出的表面 构件与形成有导电布线的基底构件的表面位于同一平面内。

公开(公告)号：US20090137085A1

公开(公告)日：2009-05-28

申请号：US12340267

申请日：2008-12-19

申请人： Jun TSUKANO ,  Kenta Ogawa ,  Takehiko Maeda ,  Shintaro Yamamichi ,  Katsumi Kikuchi

发明人： Jun TSUKANO ,  Kenta Ogawa ,  Takehiko Maeda ,  Shintaro Yamamichi ,  Katsumi Kikuchi

IPC分类号： H01L21/58

CPC分类号： H05K1/0271 ,  H01L21/4846 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/09018 ,  H05K2201/09481 ,  H05K2201/09781 ,  H01L2924/00 ,  H01L2224/0401

摘要： A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via hole formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film, the second interconnection being connected to the first interconnection via the via conductor. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via conductor, and the second interconnection are formed. The wiring substrate includes a warpage-controlling pattern on the base insulating film, and has a warped shape such that when the wiring substrate is left at rest on a horizontal plate, at least a central part of each side of a plane surface of the substrate contacts the horizontal plate, with both ends of the side raised, where each of the sides extends along a second direction perpendicular to a first direction in the plane surface of the substrate.

摘要翻译： 布线基板包括基底绝缘膜，形成在基底绝缘膜的上表面侧上的第一互连，设置在形成在基底绝缘膜中的通孔中的通孔导体，以及设置在基底绝缘膜的底面侧的第二互连 基底绝缘膜，第二互连件经由通孔导体连接到第一互连件。 布线基板包括分割的基板单元区域，其中形成有第一互连，通孔导体和第二互连。 布线基板包括在基底绝缘膜上的翘曲控制图案，并且具有翘曲形状，使得当布线基板静止在水平板上时，基板的平面的每一侧的至少中心部分 接触水平板，其侧面的两端被凸起，其中每个侧面沿着垂直于基板的平面表面中的第一方向的第二方向延伸。

公开(公告)号：US20080064147A1

公开(公告)日：2008-03-13

申请号：US11928460

申请日：2007-10-30

申请人： Toshihiro IIZUKA ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro IIZUKA ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L21/82 ,  H01L21/8242

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0

摘要翻译： 在薄膜晶体管中，上部电极和下部电极中的每一个由选自由TiN，Ti，W，WN，Pt，Ir，Ru所示的金属和金属氮化物组成的组中的至少一种形成 。 电容器电介质膜由选自ZrO 2，HfO 2 2，（Zr x x，Hf）2， （0

公开(公告)号：US20070152256A1

公开(公告)日：2007-07-05

申请号：US11637147

申请日：2006-12-12

申请人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L29/94

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： A semiconductor device having a logic section and a memory section that are formed on the same semiconductor chip, including: a first transistor formed in the logic section and having gate electrodes and source and drain regions, and a second transistor formed in the memory section having gate electrodes, source and drain regions and a capacitor, the capacitor being of a MIM structure and having an upper and a lower metal electrode and a capacitor dielectric film sandwiched therebetween, the capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO2, Hf92, (Zrx, Hf1-x)O2 (0

摘要翻译： 一种具有形成在同一半导体芯片上的逻辑部分和存储部分的半导体器件，包括：形成在逻辑部分中并具有栅电极和源极和漏极区域的第一晶体管，以及形成在存储部分中的第二晶体管， 栅极电极，源极和漏极区域以及电容器，电容器是MIM结构，并且具有夹在其间的上部和下部金属电极和电容器电介质膜，所述电容器电介质膜由介电材料形成，所述绝缘材料选自 由ZrO2，Hf92，（Zrx，Hf1-x）O2（0

公开(公告)号：US20070080439A1

公开(公告)日：2007-04-12

申请号：US11542261

申请日：2006-10-04

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K3/20 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09881 ,  H05K2201/0989 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.

摘要翻译： 一种布线板，包括：第一表面，其上设置有第一电极;第二表面，其上设置有第二电极; 至少单个绝缘层和至少一个布线层; 以及一个或多个安装的半导体元件，其中设置在第二表面上的第二电极嵌入在绝缘层中，在第二电极的第二表面侧上的暴露表面的相对侧上的表面连接到布线 层，并且第二电极的全部或部分侧面不与绝缘层接触。

公开(公告)号：US20070079987A1

公开(公告)日：2007-04-12

申请号：US11544732

申请日：2006-10-10

申请人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Yoichiro Kurita ,  Koji Soejima

发明人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Yoichiro Kurita ,  Koji Soejima

IPC分类号： H05K1/16

CPC分类号： H01L23/49816 ,  H01L21/6835 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor device comprising a flat wiring board, a first LSI disposed on one surface of the wiring board, a sealing resin for covering the one surface and a side face of the first semiconductor element, and a second LSI disposed on another surface of the wiring board. The wiring board has conductive wiring as a wiring layer, an insulation resin as a support layer for the wiring layer, and a conductive through-hole that passes through the wiring layer and the support layer. Connection points between lands disposed in positions in which the external peripheral edges of the semiconductor elements transverse the interior of the lands as viewed vertically from above, which lands are selected from land portions on which the external connection terminals are formed, and the wiring board formed in the same plane as the lands, are unevenly distributed toward one side of the wiring board. Connections for very small wiring are thereby made possible, and a plurality of semiconductor elements can be very densely connected.

摘要翻译： 一种半导体器件，包括平面布线板，布置在所述布线板的一个表面上的第一LSI，用于覆盖所述一个表面的密封树脂和所述第一半导体元件的侧面，以及设置在所述布线的另一个表面上的第二LSI 板。 布线基板具有作为布线层的导电布线，作为布线层的支撑层的绝缘树脂，以及穿过布线层和支撑层的导电性通孔。 半导体元件的外周边缘从上方垂直观察到的焊盘的内部的位置之间的连接点，其中所述焊盘从形成有外部连接端子的焊盘部分选择，并且形成了布线板 在与地面相同的平面中，不均匀地分布在布线板的一侧。 由此，可以实现非常小的布线的连接，并且可以非常密集地连接多个半导体元件。