公开(公告)号：US20050040508A1

公开(公告)日：2005-02-24

申请号：US10798943

申请日：2004-03-12

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/12 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L21/48 ,  H01L23/52

CPC分类号： H01L23/4985 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package stack has at least two packages of area array types (AAT), each having connecting pads. A flexible cable having conductive patterns is provided between the AAT packages and electrically connected to the connecting pads of the packages.

摘要翻译： 封装堆栈具有至少两个区域阵列类型（AAT）封装，每个封装具有连接焊盘。 具有导电图案的柔性电缆设置在AAT封装之间并电连接到封装的连接焊盘。

公开(公告)号：US08604616B2

公开(公告)日：2013-12-10

申请号：US13357743

申请日：2012-01-25

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/525 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/12 ,  H01L24/16 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/06136 ,  H01L2224/13009 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/4824 ,  H01L2224/83851 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/29075 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack thereof, a semiconductor device package thereof, and an electronic apparatus having the same are disclosed. The semiconductor chip comprising, a substrate including an inner semiconductor circuit, a conductive redistribution structure formed on the substrate including a conductive redistribution interconnection and a conductive redistribution via plug, wherein the redistribution via plug is connected to the inner semiconductor circuit; a conductive chip pad formed on the substrate, and a conductive chip via plug configured to penetrate the substrate and electrically connected to the redistribution structure.

摘要翻译： 公开了一种半导体芯片，其包括穿过基板的芯片通孔插塞，其半导体叠层，其半导体器件封装以及具有该半导体芯片的电子设备。 所述半导体芯片包括：包括内部半导体电路的基板，形成在所述基板上的导电再分布结构，所述导电再分布结构包括导电再分配互连和通过插头的导电再分布，其中所述再分配经由插头连接到所述内部半导体电路; 形成在所述基板上的导电芯片焊盘，以及被配置为穿透所述基板并电连接到所述再分布结构的导电芯片通孔插头。

公开(公告)号：US08319351B2

公开(公告)日：2012-11-27

申请号：US12689717

申请日：2010-01-19

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/18 ,  H01L23/481 ,  H01L24/02 ,  H01L24/12 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Provided are a planar multi semiconductor chip package in which a processor and a memory device are connected to each other via a through electrode and a method of manufacturing the planar multi semiconductor chip package. The planar multi semiconductor chip package includes: a substrate comprising a plurality of first circuit patterns on a first surface and a plurality of second circuit patterns on a second surface; a first semiconductor chip comprising a plurality of memory devices arranged on the substrate, wherein first memory devices surround at least a portion of second memory devices; a second semiconductor chip stacked on the first semiconductor chip and corresponding to the second memory devices; and a plurality of through electrodes arranged on the second memory devices and connecting the first and second semiconductor chips to the second circuit pattern of the substrate.

摘要翻译： 提供一种平面多半导体芯片封装，其中处理器和存储器件经由通孔彼此连接，以及制造平面多芯片封装的方法。 平面多晶半导体芯片封装包括：在第一表面上包括多个第一电路图案的基板和在第二表面上的多个第二电路图案; 包括布置在所述基板上的多个存储器件的第一半导体芯片，其中第一存储器件围绕第二存储器件的至少一部分; 堆叠在第一半导体芯片上并对应于第二存储器件的第二半导体芯片; 以及布置在第二存储器件上并将第一和第二半导体芯片连接到基板的第二电路图案的多个贯通电极。

公开(公告)号：US20120064827A1

公开(公告)日：2012-03-15

申请号：US13229193

申请日：2011-09-09

申请人： Yong-Hoon KIM ,  Jong-Joo Lee ,  Sang-Youb Lee ,  Young-Don Choi ,  Hee-Seok Lee

发明人： Yong-Hoon KIM ,  Jong-Joo Lee ,  Sang-Youb Lee ,  Young-Don Choi ,  Hee-Seok Lee

IPC分类号： H04B5/00

CPC分类号： H01L23/645 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H04B5/0012 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0075 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

摘要翻译： 公开了一种包括通孔的半导体器件。 半导体器件可以包括第一半导体芯片，其包括形成在第一表面上的收发器电路，形成在与第一表面相对的第二表面上的第一耦合导体图案，以及连接收发器电路和第一耦合导电 模式。 可以存在位于第二半导体芯片上的收发器，并且包括面向与第一耦合导电图案无线通信的第一耦合导电图案的第二耦合导电图案。

公开(公告)号：US08061024B2

公开(公告)日：2011-11-22

申请号：US12126364

申请日：2008-05-23

申请人： Jong-Joo Lee ,  Soon-Yong Hur

发明人： Jong-Joo Lee ,  Soon-Yong Hur

IPC分类号： H05K3/02

CPC分类号： H05K3/242 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/15311 ,  H05K1/111 ,  H05K3/064 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/10674 ,  H05K2203/0574 ,  H05K2203/175 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Provided are a circuit board, a semiconductor package including the circuit board, a method of fabricating the circuit board, and a method of fabricating the semiconductor package. The method of fabricating the circuit board includes: forming at least one pair of rows of first bonding pads arranged on a base substrate in a first direction, and a first central plating line formed between the rows of first bonding pads to commonly connect with the rows of first bonding pads; forming an electroplating layer on the first bonding pads; and exposing the base substrate by removing the first central plating line.

摘要翻译： 提供了一种电路板，包括电路板的半导体封装，制造电路板的方法以及制造半导体封装的方法。 制造电路板的方法包括：在第一方向上形成布置在基底基板上的至少一对第一接合焊盘列，以及形成在第一接合焊盘行之间的第一中心电镀线，以与行共同连接 的第一粘接垫; 在所述第一接合焊盘上形成电镀层; 并且通过去除第一中心电镀线来暴露基底。

公开(公告)号：US20100230811A1

公开(公告)日：2010-09-16

申请号：US12722794

申请日：2010-03-12

申请人： Dong-Kil Shin ,  Shle-Ge Lee ,  Jong-Joo Lee ,  Jong-Ho Lee

发明人： Dong-Kil Shin ,  Shle-Ge Lee ,  Jong-Joo Lee ,  Jong-Ho Lee

IPC分类号： H01L23/498

CPC分类号： H01L24/13 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/11464 ,  H01L2224/13006 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

摘要： In one embodiment, a semiconductor device includes a semiconductor substrate and a bonding pad disposed thereon. The semiconductor device also includes a passivation layer, a buffer layer, and an insulating layer sequentially stacked on the semiconductor substrate. According to one aspect, a first recess is defined within the passivation layer, the buffer layer, and the insulating layer to expose at least a region of the bonding pad and a second recess is defined within the insulating layer to expose at least a region of the buffer layer and spaced apart from the first recess such that a portion of the insulating layer is interposed therebetween. Further, the semiconductor device includes a conductive solder bump disposed within the first and second recesses. The conductive solder bump may be connected to the bonding pad in the first recess and supported by the buffer layer through a protrusion of the conductive solder bump extending into the second recess.

摘要翻译： 在一个实施例中，半导体器件包括半导体衬底和设置在其上的接合焊盘。 半导体器件还包括依次堆叠在半导体衬底上的钝化层，缓冲层和绝缘层。 根据一个方面，在钝化层，缓冲层和绝缘层内限定第一凹槽，以露出焊盘的至少一个区域，并且在绝缘层内限定第二凹槽，以暴露至少一个区域 缓冲层，并且与第一凹部间隔开，使得绝缘层的一部分插入其间。 此外，半导体器件包括设置在第一和第二凹槽内的导电焊料凸块。 导电焊料凸块可以连接到第一凹槽中的焊盘，并且通过延伸到第二凹部中的导电焊料凸块的突起被缓冲层支撑。

公开(公告)号：US07545037B2

公开(公告)日：2009-06-09

申请号：US11378899

申请日：2006-03-17

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/52

CPC分类号： H01L23/5286 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/1203 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/05552

摘要： Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

摘要翻译： 提供了具有直接连接到内部电路的电源/接地线的重分布金属互连的半导体芯片的实施例。 半导体芯片的实施例包括形成在半导体衬底上的内部电路。 芯片焊盘设置在半导体衬底上。 芯片焊盘通过内部互连电连接到内部电路。 钝化层设置在芯片焊盘的上方。 在钝化层上设置重新分布的金属互连。 再分布的金属互连通过穿孔至少钝化层的通孔和芯片焊盘开口将内部互连直接连接到芯片焊盘。 还提供了制造半导体芯片的方法。

公开(公告)号：US20070278657A1

公开(公告)日：2007-12-06

申请号：US11710490

申请日：2007-02-26

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/485 ,  H01L21/50 ,  H01L23/52

CPC分类号： H01L21/76898 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17517 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/81136 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip stack may include a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. Each semiconductor chip may have an active surface, a back surface opposite to the active surface, and a plurality of connection pads arranged in the center of the active surface. At least one through electrode may be formed in the first semiconductor chip and may be connected to at least one of the plurality of connection pads, and a portion of the at least one through electrode may be exposed by the back surface of the first semiconductor chip. The active surface of the first semiconductor chip may be arranged to face the active surface of the second semiconductor chip. The plurality of connection pads of the first semiconductor chip may be electrically connected to the plurality of connection pads of the second semiconductor chip.

摘要翻译： 芯片堆叠可以包括堆叠在第一半导体芯片上的第一半导体芯片和第二半导体芯片。 每个半导体芯片可以具有有源表面，与有源表面相对的后表面，以及布置在有源表面的中心的多个连接焊盘。 至少一个贯通电极可以形成在第一半导体芯片中并且可以连接到多个连接焊盘中的至少一个，并且至少一个贯通电极的一部分可以被第一半导体芯片的背面曝光 。 第一半导体芯片的有源表面可以布置成面对第二半导体芯片的有源表面。 第一半导体芯片的多个连接焊盘可以电连接到第二半导体芯片的多个连接焊盘。

公开(公告)号：US20070040247A1

公开(公告)日：2007-02-22

申请号：US11503269

申请日：2006-08-14

申请人： Jong-Joo Lee ,  Mee-Hyun Ahn

发明人： Jong-Joo Lee ,  Mee-Hyun Ahn

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L23/49513 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/078 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention provides a variety of leadframe packages in which signal connections and fixed voltage connections are configured differently to improve the relative performance of the connections relative to their assigned function. The signal connections incorporate one or more configurations of signal lead and corresponding signal bonding wires that tend to reduce the relative capacitance of the signal connectors and thereby improve high speed performance. The fixed voltage connections incorporate configurations of fixed voltage leads and fixed voltage bonding wires that will tend to reduce the inductance of the fixed voltage connector and reduce noise on the fixed voltage connections and improve power delivery characteristics. The configurations of the associated signal and fixed voltage connections will tend to result in signal connections that include signal leads that are shorter, narrower and/or more widely separated from the active surface of the semiconductor chip than the corresponding fixed voltage leads.

摘要翻译： 本发明提供了各种引线框封装，其中信号连接和固定电压连接被配置为不同以改善连接相对于其分配的功能的相对性能。 信号连接包括一个或多个信号引线和对应的信号接合线的配置，其倾向于减小信号连接器的相对电容，从而提高高速性能。 固定电压连接包括固定电压引线和固定电压接合线的配置，这将降低固定电压连接器的电感，并降低固定电压连接上的噪声，并提高功率输送特性。 相关联的信号和固定电压连接的配置将趋于导致信号连接，其包括与相应的固定电压引线相比更短，更窄和/或更广泛地与半导体芯片的有源表面分离的信号引线。

公开(公告)号：US20070029662A1

公开(公告)日：2007-02-08

申请号：US11335523

申请日：2006-01-20

申请人： Jong-Joo Lee

发明人： Jong-Joo Lee

IPC分类号： H01L23/52

CPC分类号： H01L23/5228 ,  H01L23/5225 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device may have a plurality of dielectric layers and at least one termination circuit line between the dielectric layers. The termination circuit lines may be formed over the active surface of a semiconductor substrate.

摘要翻译： 半导体器件可以具有多个电介质层和介电层之间的至少一个终端电路线。 终端电路线可以形成在半导体衬底的有源表面上。