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    CHIP SCALE SENSING CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF
    31.
    发明申请
    CHIP SCALE SENSING CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF 审中-公开
    芯片尺寸感应芯片包装及其制造方法

    公开(公告)号：US20160266680A1

    公开(公告)日：2016-09-15

    申请号：US15061858

    申请日：2016-03-04

    Applicant: XINTEC INC.

    Inventor： Shu-Ming CHANG ,  Yu-Lung HUANG ,  Tsang-Yu LIU ,  Yen-Shih HO

    IPC: G06F3/044 ,  H01L21/52 ,  G06F21/32 ,  H01L21/56 ,  H01L23/544 ,  H01L21/78 ,  H01L21/768 ,  H01L23/31

    CPC classification number: G06F3/044 ,  G06F2203/04103 ,  G06K9/00006 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L2221/68327 ,  H01L2224/11

    Abstract: This present invention provides a chip scale sensing chip package, comprising a sensing chip having a first top surface and a first bottom surface opposite to each other, a touch plate having a second top surface and a second bottom surface opposite to each other, formed above the sensing chip, and a color layer, sandwiched between the sensing chip and the touch plate, wherein the sensing chip comprises a sensing device formed nearby the first top surface and a plurality of conductive pads formed nearby the first top surface and adjacent to the sensing device, a plurality of through silicon vias exposing their corresponding conductive pads formed on the first bottom surface, a plurality of conductive structures formed on the first bottom surface, and a re-distribution layer overlaying the first bottom surface and each through silicon via to electrically connect each conductive pad and each conductive structure.

    Abstract translation: 本发明提供了一种芯片级感测芯片封装，包括具有彼此相对的第一顶表面和第一底表面的感测芯片，具有彼此相对的第二顶表面和第二底表面的触摸板， 感测芯片和夹在感测芯片和触摸板之间的彩色层，其中感测芯片包括在第一顶表面附近形成的感测装置，以及在第一顶表面附近形成并邻近感测的多个导电焊盘 多个通孔硅通孔，暴露其形成在第一底表面上的相应的导电焊盘，形成在第一底表面上的多个导电结构，以及覆盖第一底表面和每个穿过硅通孔的再分配层， 连接每个导电焊盘和每个导电结构。

    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    35.
    发明申请
    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    半导体结构及其制造方法

    公开(公告)号：US20140252659A1

    公开(公告)日：2014-09-11

    申请号：US14199640

    申请日：2014-03-06

    Applicant: XINTEC INC.

    Inventor： Yung-Tai TSAI ,  Shu-Ming CHANG ,  Chun-Wei CHANG ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Yen-Shih HO

    IPC: H01L23/00

    CPC classification number: H01L24/05 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/03 ,  H01L2224/02371 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00014

    Abstract: A semiconductor structure includes a wafer, at least one nonmetal oxide layer, a pad, a passivation layer, an isolation layer, and a conductive layer. The wafer has a first surface, a second surface, a third surface, a first stage difference surface connected between the second and third surfaces, and a second stage difference surface connected between the first and third surfaces. The nonmetal oxide layer is located on the first surface of the wafer. The pad is located on the nonmetal oxide layer and electrically connected to the wafer. The passivation layer is located on the nonmetal oxide layer. The isolation layer is located on the passivation layer, nonmetal oxide layer, the first, second and third surfaces of the wafer, and the first and second stage difference surfaces of the wafer. The conductive layer is located on the isolation layer and electrically contacts the pad.

    Abstract translation: 半导体结构包括晶片，至少一个非金属氧化物层，焊盘，钝化层，隔离层和导电层。 晶片具有连接在第二和第三表面之间的第一表面，第二表面，第三表面，第一阶段差异表面以及连接在第一和第三表面之间的第二阶段差异表面。 非金属氧化物层位于晶片的第一表面上。 垫位于非金属氧化物层上并电连接到晶片。 钝化层位于非金属氧化物层上。 隔离层位于钝化层，非金属氧化物层，晶片的第一，第二和第三表面以及晶片的第一和第二级差分表面上。 导电层位于隔离层上并电接触焊盘。

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    38.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
    芯片包装及其形成方法

    公开(公告)号：US20130320559A1

    公开(公告)日：2013-12-05

    申请号：US13900081

    申请日：2013-05-22

    Applicant: XINTEC INC.

    Inventor： Yu-Ting HUANG ,  Shu-Ming CHANG ,  Yen-Shih HO ,  Tsang-Yu LIU

    IPC: B81B7/00

    CPC classification number: B81B7/0077 ,  B81B7/007 ,  B81B2207/095 ,  B81B2207/096 ,  H01L21/64 ,  H01L23/481 ,  H01L23/498 ,  H01L23/525 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06182 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

    Abstract: An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate.

    Abstract translation: 本发明的实施例提供一种芯片封装，包括：第一半导体衬底; 设置在所述第一半导体衬底上的第二半导体衬底，其中所述第二半导体衬底包括下半导体层，上半导体层和位于所述下半导体层和所述上半导体层之间的绝缘层，以及所述下半导体 层与第一半导体衬底上的至少焊盘电接触; 信号导通结构，设置在所述第一半导体衬底的下表面上，其中所述信号导电结构电连接到所述第一半导体衬底上的信号焊盘; 以及导电层，其设置在所述第二半导体衬底的所述上半导体层上并与所述下半导体层的与所述第一半导体衬底上的所述至少一个焊盘电接触的部分电接触。

    MANUFACTURING METHOD OF CHIP PACKAGE
    39.
    发明申请
    MANUFACTURING METHOD OF CHIP PACKAGE 有权

    公开(公告)号：US20210066379A1

    公开(公告)日：2021-03-04

    申请号：US16950810

    申请日：2020-11-17

    Applicant: XINTEC INC.

    Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Po-Han LEE

    IPC: H01L27/146 ,  H01L23/00

    Abstract: A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    40.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 审中-公开

    公开(公告)号：US20180102321A1

    公开(公告)日：2018-04-12

    申请号：US15724058

    申请日：2017-10-03

    Applicant: XINTEC INC.

    Inventor： Yen-Shih HO ,  Po-Han LEE ,  Chia-Ming CHENG ,  Hsin-Yen LIN

    IPC: H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/495 ,  H01L23/00

    Abstract: A chip package including a substrate having an upper surface, a lower surface, and a sidewall surface that is at the edge of the substrate is provided. The substrate includes a sensor device therein and adjacent to the upper surface thereof. The chip package further includes light-shielding layer disposed over the sidewall surface of the substrate and extends along the edge of the substrate to surround the sensor device. The chip package further includes a cover plate disposed over the upper surface of the substrate and a spacer layer disposed between the substrate and the cover plate. A method of forming the chip package is also provided.

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