公开(公告)号：US20240290683A1

公开(公告)日：2024-08-29

申请号：US18114362

申请日：2023-02-27

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Wen-Yi LIN ,  Kuang-Chun LEE ,  Chien-Chen LI ,  Chien-Li KUO ,  Kuo-Chio LIU

IPC分类号： H01L23/373 ,  H01L21/48 ,  H01L23/053 ,  H01L23/367

CPC分类号： H01L23/3732 ,  H01L21/4871 ,  H01L23/053 ,  H01L23/3672 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253

摘要： An embodiment semiconductor package structure may include a package substrate, a semiconductor die coupled to the package substrate, and a package lid attached to the package substrate and covering the semiconductor die. The package lid may include a top portion having a spatially varying thermal conductivity that is greater in a first region than in a second region. The first region may include a multi-layer structure including a metal/diamond composite material supported by a copper layer. The metal/diamond composite material may include a silver/diamond, copper/diamond, or aluminum/diamond material and may have a thermal conductivity that is within a range from 600 W/m·K to 900 W/m·K and a coefficient of thermal expansion that is in a second range from 5 ppm/° C. to 10 ppm/° C. The package lid may have an effective coefficient of thermal expansion that is in a range from 14.5 ppm/° C. to 17 ppm/° C.

公开(公告)号：US20240282749A1

公开(公告)日：2024-08-22

申请号：US18652832

申请日：2024-05-02

申请人： ROHM CO., LTD.

发明人： Yuki NAKANO

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L25/0655 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/48137 ,  H01L2224/48155 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/182

摘要： A semiconductor device includes a chip that has a main surface, a main surface electrode that covers the main surface, pillar electrodes that are arranged on the main surface electrode at an interval, a sealing insulator that covers a region between the pillar electrodes on the main surface electrode such as to expose parts of the pillar electrodes, and at least one terminal film that covers at least one of the pillar electrodes on the sealing insulator.

公开(公告)号：US20240282672A1

公开(公告)日：2024-08-22

申请号：US18389251

申请日：2023-11-14

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： BONGWEE YU ,  KYOUNG -MIN LEE ,  KYUNGSOO LEE ,  JUNHO HUH

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L25/10 ,  H10B80/00

CPC分类号： H01L23/481 ,  H01L23/528 ,  H01L24/16 ,  H01L25/105 ,  H10B80/00 ,  H01L24/14 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225

摘要： A semiconductor device includes: a package substrate; a first die on the package substrate and including a hard macro and through silicon vias; and a second die on the first die, wherein the first die includes a first region, which does not include the hard macro, and a second region including a macro-region that includes the hard macro, wherein the through silicon vias of the first region are arranged in a first direction with a first distance and in a second direction with a second distance, wherein the through silicon vias of the second region are arranged in the first direction with a first pitch, and in the second direction with a second pitch, wherein the macro-region is interposed between the through silicon vias arranged in the first direction, wherein the first pitch is greater than the first distance, and wherein the second pitch is less than the second distance.

公开(公告)号：US20240282658A1

公开(公告)日：2024-08-22

申请号：US18169998

申请日：2023-02-16

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： John Knickerbocker ,  Mukta Ghate Farooq ,  Keiji Matsumoto

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/367

CPC分类号： H01L23/3185 ,  H01L21/561 ,  H01L23/29 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/3675 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/95 ,  H01L2224/16225 ,  H01L2224/2732 ,  H01L2224/2741 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/2783 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29181 ,  H01L2224/29186 ,  H01L2224/2919 ,  H01L2224/32153 ,  H01L2224/32221 ,  H01L2224/33183 ,  H01L2224/95 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/04953 ,  H01L2924/07025

摘要： A semiconductor integrated circuit device includes a first back-end-of-line region coupled to a first side of a front-end-of-line region, a second back-end-of-line region coupled to a second side of the front-end-of-line region, and a thermally conducting solder at least partially surrounding a perimeter of the front-end-of-line region, the first back-end-of-line region and the second back-end-of-line region.

公开(公告)号：US12068172B2

公开(公告)日：2024-08-20

申请号：US16525985

申请日：2019-07-30

申请人： Intel Corporation

发明人： Tarek A. Ibrahim ,  Rahul N. Manepalli ,  Wei-Lun K. Jen ,  Steve S. Cho ,  Jason M. Gamba ,  Javier Soto Gonzalez

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01L21/4846 ,  H01L21/481 ,  H01L23/49838 ,  H01L23/5386 ,  H01L23/5385 ,  H01L2224/16225 ,  H01L2924/19041 ,  H01L2924/19105

摘要： Embodiments disclosed herein include electronic packages and methods of making electronic packages. In an embodiment, the electronic package comprises a package substrate, an array of first level interconnect (FLI) bumps on the package substrate, wherein each FLI bump comprises a surface finish, a first pad on the package substrate, wherein the first pad comprises the surface finish, and wherein a first FLI bump of the array of FLI bumps is electrically coupled to the first pad, and a second pad on the package substrate, wherein the second pad is electrically coupled to the first pad.

公开(公告)号：US12062622B2

公开(公告)日：2024-08-13

申请号：US17883568

申请日：2022-08-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Han-Ping Pu ,  Hsiao-Wen Lee

IPC分类号： H01L23/538 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/5389 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76895 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2221/68359 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13024 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01029 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025

摘要： The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

公开(公告)号：US20240266266A1

公开(公告)日：2024-08-08

申请号：US18322735

申请日：2023-05-24

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Kuo-Ching Hsu ,  Hsiang-Tai Lu ,  Kuan-Lung Wu ,  Ya Huei Lee

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06541

摘要： A semiconductor structure includes: an interposer including an integrated passive device, a die-side redistribution structure, first on-interposer bump structures, and second on-interposer bump structures. First die-side redistribution wiring interconnects electrically connect electrical nodes within the integrated passive device to the first on-interposer bump structures. Second die-side redistribution wiring interconnects provide a respective electrical connection between a respective pair of second on-interposer bump structures. A first semiconductor die includes first on-die bump structures that are bonded to the first on-interposer bump structures through first solder material portions, and further includes second on-die bump structures that are bonded to the second on-interposer bump structures through second solder material portions. The first semiconductor die includes first metal interconnect structures providing electrical connections between a respective one of the first on-interposer bump structures and a respective one of the second on-interposer bump structures.

公开(公告)号：US12058806B2

公开(公告)日：2024-08-06

申请号：US17692486

申请日：2022-03-11

申请人： SKYWORKS SOLUTIONS, INC.

发明人： Shaul Branchevsky ,  Howard E. Chen ,  Anthony James Lobianco

IPC分类号： H05K1/02 ,  H01L23/00 ,  H01L23/06 ,  H01L23/15 ,  H01L23/29 ,  H01L23/50 ,  H01L23/552 ,  H01L23/60 ,  H01L23/66 ,  H05K1/03 ,  H05K1/11 ,  H05K1/16 ,  H05K1/18 ,  H05K3/00 ,  H05K3/12 ,  H05K3/20 ,  H05K3/22 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H01L23/31 ,  H01L23/498

CPC分类号： H05K1/0216 ,  H01L23/06 ,  H01L23/552 ,  H01L24/94 ,  H05K1/0215 ,  H05K1/0218 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/181 ,  H05K3/005 ,  H05K3/1241 ,  H05K3/22 ,  H05K3/403 ,  H05K3/429 ,  H05K3/4644 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19105 ,  H05K3/0052 ,  H05K3/4629 ,  H05K2201/0715 ,  H05K2201/0919 ,  H05K2201/09563 ,  H05K2201/10098 ,  H05K2201/10674 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

摘要： Devices and methods related to metallization of ceramic substrates for shielding applications. In some embodiments, a ceramic assembly includes a plurality of layers, the assembly including a boundary between a first region and a second region, the assembly further including a selected layer having a plurality of conductive features along the boundary, each conductive feature extending into the first region and the second region such that when the first region and the second region are separated to form their respective side walls, each side wall includes exposed portions of the conductive features capable of forming electrical connection with a conductive shielding layer.

公开(公告)号：US12057413B2

公开(公告)日：2024-08-06

申请号：US16393047

申请日：2019-04-24

申请人： Intel Corporation

发明人： Lijiang Wang ,  Jianyong Xie ,  Arghya Sain ,  Xiaohong Jiang ,  Sujit Sharan ,  Kemal Aygun

IPC分类号： H01L23/66 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/66 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2924/30111

摘要： Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.

公开(公告)号：US12051680B2

公开(公告)日：2024-07-30

申请号：US17735158

申请日：2022-05-03

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Tae Hwan Kim ,  Hyung Gil Baek ,  Young-Ja Kim ,  Kang Gyune Lee ,  Sang-Won Lee ,  Yong Kwan Lee

IPC分类号： H01L25/16 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L25/162 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/165 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/165 ,  H01L2924/1659 ,  H01L2924/182

摘要： A semiconductor package may include; a first substrate, a first semiconductor chip disposed on the first substrate, an interposer disposed on the first semiconductor chip, a connecter spaced apart from the first semiconductor chip in a first horizontal direction and extending between the first substrate and the interposer, wherein the connecter directly electrically connects the first substrate and the interposer, a capacitor disposed between the connecter and the first semiconductor chip, and a guide pattern including a first guide portion and an opposing second guide portion spaced apart in the first horizontal direction, wherein the first guide portion is disposed between the connecter and the capacitor, the second guide portion is disposed between the capacitor and the first semiconductor chip, and at least part of the capacitor is inserted between the first guide portion and the second guide portion.