公开(公告)号：US20090261461A1

公开(公告)日：2009-10-22

申请号：US12104182

申请日：2008-04-16

Applicant: Steven Sapp ,  Chung-Lin Wu ,  Maria Christina B. Estacio ,  Bigildis Dosdos ,  Hamza Yilmaz

Inventor： Steven Sapp ,  Chung-Lin Wu ,  Maria Christina B. Estacio ,  Bigildis Dosdos ,  Hamza Yilmaz

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L23/49562 ,  H01L23/49524 ,  H01L23/49548 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/37147 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599 ,  H01L2924/206

Abstract: Semiconductor packages comprising a plurality of lead fingers containing a lead intrusion at the edge of the lead fingers are described. The semiconductor packages comprise an integrated circuit chip that is connected to a die pad and is electrically connected to multiple lead fingers. One or more of the lead fingers may have a lead intrusion disposed on the external exposed lower surface of the lead finger. The lead intrusion may have a height that is about ⅕ to about ½ the height of a lead finger, a width that is about ⅕ to about 1/2 the width of a lead finger, and a depth that is about ¼ to about ¾ the length of the externally exposed lower surface of a lead finger. The lead intrusion increases the area on the lead finger that contacts a bond material, such as solder, and therefore increase the strength of the joint between the semiconductor package and an external surface to which the lead finger is connected (i.e., a PCB). The lead intrusion allows out gassing during reflow of the bond material which may reduce voiding. The lead intrusion can also increase bond joint reliability by providing longer crack propagation length.

Abstract translation: 描述了包括在引线的边缘处包含铅侵入的多个引线指的半导体封装。 半导体封装包括连接到管芯焊盘并且电连接到多个引线指的集成电路芯片。 一个或多个引导指可以具有设置在引线指的外部暴露下表面上的引线侵入。 引线入侵可以具有引导指的高度的约1/5至约1/2的高度，宽度是引线指的宽度的大约1/5至大约1/2，并且深度约为1/4 到铅笔的外部暴露的下表面的长度的约3/4。 引线入侵增加了引线接触诸如焊料的接合材料的引线区域，因此增加了半导体封装与引线指连接的外表面（即PCB）之间的接合强度。 铅侵入允许在回流焊接材料期间放气，这可能减少空隙。 铅侵入也可以通过提供更长的裂纹扩展长度来增加接合点的可靠性。

公开(公告)号：US20090224401A1

公开(公告)日：2009-09-10

申请号：US12398049

申请日：2009-03-04

Applicant: Seiya FUJII

Inventor： Seiya FUJII

IPC: H01L23/498 ,  H01L21/50

CPC classification number: H01L23/49833 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/078 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

Abstract: A semiconductor device comprises a package substrate, a semiconductor chip, a plurality of bump electrodes and one or more dummy chips. The semiconductor chip is mounted on one surface of the package substrate. The bump electrodes are the other surface of the package substrate and electrically connected to the semiconductor chip through a wiring structure. Each of the dummy chips is mounted on a predetermined region close to a corner portion of the semiconductor chip on the one surface of the package substrate.In the semiconductor chip, the dummy chips are formed of material having the same or similar coefficient of thermal expansion as that of the semiconductor chip. Therefore the stress caused by a difference between coefficients of thermal expansion is suppressed so as to improve connection reliability.

Abstract translation: 半导体器件包括封装衬底，半导体芯片，多个凸起电极和一个或多个虚拟芯片。 半导体芯片安装在封装基板的一个表面上。 突起电极是封装基板的另一个表面，并通过布线结构与半导体芯片电连接。 每个虚拟芯片安装在封装基板的一个表面上靠近半导体芯片的角部的预定区域上。 在半导体芯片中，虚设芯片由与半导体芯片相同或相似的热膨胀系数的材料形成。 因此，抑制由热膨胀系数之间的差异引起的应力，从而提高连接可靠性。

公开(公告)号：US20090212423A1

公开(公告)日：2009-08-27

申请号：US12196210

申请日：2008-08-21

Applicant: Junji TANAKA ,  Masahiko HARAYAMA ,  Masanori ONODERA

Inventor： Junji TANAKA ,  Masahiko HARAYAMA ,  Masanori ONODERA

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H05K3/38 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2225/06568 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/20752 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/1025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device is provided that includes a semiconductor chip, a plurality of solder bumps that electrically couple the semiconductor chip to the outside, and a metal bump being provided on the surface of each first solder bump which is at least a part of the plurality of solder bumps and being made of a metal having a melting point higher than that of the first solder bump. The wettability of the first solder bump is improved as each metal bump serves as a core when the corresponding first solder bump melts. Thus, the connection reliability of the first solder bump can be improved.

Abstract translation: 提供了一种半导体器件，其包括半导体芯片，将半导体芯片电耦合到外部的多个焊料凸块以及设置在每个第一焊料凸块的表面上的金属凸块，该第一焊料凸块是至少部分多个 焊料凸起并且由熔点高于第一焊料凸点的金属制成。 当相应的第一焊料凸块熔化时，每个金属凸块用作芯时，第一焊料凸块的润湿性得到改善。 因此，可以提高第一焊料凸块的连接可靠性。

公开(公告)号：US20090194889A1

公开(公告)日：2009-08-06

申请号：US12026312

申请日：2008-02-05

Applicant: Shin-Puu Jeng ,  Yu-Wen Liu ,  Hao-Yi Tsai ,  Hsien-Wei Chen

Inventor： Shin-Puu Jeng ,  Yu-Wen Liu ,  Hao-Yi Tsai ,  Hsien-Wei Chen

IPC: H01L23/485

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive structure. In an embodiment, the contiguous conductive structure is a solid layer of conductive material. In other embodiments, the contiguous conductive structure is a conductive network including, for example, a matrix configuration or a plurality of conductive stripes. At least one dielectric spacer may interpose the conductive network. In an embodiment, the conductive density of the connective layer is between approximately 20% and 100%.

Abstract translation: 提供了一种焊盘结构，其包括两个导电层和插入两个导电层的连接层。 连接层包括连续的导电结构。 在一个实施例中，邻接的导电结构是导电材料的固体层。 在其它实施例中，连续导电结构是包括例如矩阵配置或多个导电条纹的导电网络。 至少一个电介质间隔物可以插入导电网络。 在一个实施例中，连接层的导电密度在大约20％和100％之间。

公开(公告)号：US07557454B2

公开(公告)日：2009-07-07

申请号：US11182160

申请日：2005-07-15

Applicant: Todd O. Bolken

Inventor： Todd O. Bolken

IPC: H01L23/49 ,  H01L23/495

CPC classification number: H01L23/4952 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48092 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor device includes two or more semiconductor devices with bond pads that are electrically connected to the same, single surface of a plurality of leads. The two or more devices may include substantially centrally located bond pads or substantially identically arranged bond pads.

Abstract translation: 半导体器件包括两个或更多个具有接合焊盘的半导体器件，该焊盘电连接到多个引线的相同的单个表面。 两个或更多个器件可以包括基本上位于中心的接合焊盘或基本相同布置的接合焊盘。

公开(公告)号：US20090098687A1

公开(公告)日：2009-04-16

申请号：US11973859

申请日：2007-10-10

Applicant: Joze Eura Antol ,  John William Osenbach ,  Ronald James Weachock

Inventor： Joze Eura Antol ,  John William Osenbach ,  Ronald James Weachock

IPC: H01L21/603

CPC classification number: H01L24/85 ,  H01L24/05 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/83 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05073 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/2919 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/4807 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48451 ,  H01L2224/48463 ,  H01L2224/48482 ,  H01L2224/48624 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83 ,  H01L2224/85051 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2224/859 ,  H01L2224/8592 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0106 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01202 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/00014 ,  H01L2224/48465 ,  H01L2924/0665 ,  H01L2924/00

Abstract: It has been found that integrated packages having dies with at least 10 bonding pads separated by a pitch of 65 μm or less are susceptible to corrosion upon wire bonding to these pads and subsequent encapsulation in a passivating material. In particular, crevices are potentially formed between the bonding wire and bonding pad that are not passivated and that promote corrosion. Avoidance of crevice formation through, for example, appropriately choosing the bonding pad and wire configuration substantially avoids such corrosion.

Abstract translation: 已经发现，具有至少10个键合垫的间隔为65μm或更小的模具的集成封装在引线接合到这些焊盘并随后封装在钝化材料中时易于腐蚀。 特别地，在不被钝化并促进腐蚀的接合线和接合焊盘之间潜在地形成缝隙。 例如通过适当地选择接合焊盘和电线配置来避免缝隙形成基本上避免了这种腐蚀。

公开(公告)号：US20090057898A1

公开(公告)日：2009-03-05

申请号：US12195619

申请日：2008-08-21

Applicant: Eiji TAKAIKE

Inventor： Eiji TAKAIKE

IPC: H01L23/498 ,  H01L21/50

CPC classification number: H01L23/3121 ,  H01L21/485 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/5382 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/91 ,  H01L25/0652 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05644 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20105 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An insulating layer having an opening from which an electrode pad of a device is exposed is formed on the surface of a semiconductor substrate having the device fabricated therein, and an external terminal pad defined by a portion of a conductor layer formed on the insulating layer is connected to the electrode pad by means of a bonding wire. Further, a conductor post is formed on the external terminal pad, and an encapsulation resin layer is formed to coat a region on the semiconductor substrate in which the conductor post is formed, and to expose a top portion of the conductor post. An external connecting terminal is bonded to the top portion of the conductor post.

Abstract translation: 在具有制造器件的半导体衬底的表面上形成具有开口的绝缘层，其中器件的电极焊盘露出，并且由形成在绝缘层上的导体层的一部分限定的外部端子焊盘是 通过接合线连接到电极焊盘。 此外，在外部端子焊盘上形成导体柱，并且形成封装树脂层以涂覆形成导体柱的半导体衬底上的区域，并露出导体柱的顶部。 外部连接端子接合到导体柱的顶部。

公开(公告)号：US20080284003A1

公开(公告)日：2008-11-20

申请号：US11767889

申请日：2007-06-25

Applicant: Chua Swee Kwang ,  Chia Yong Poo

Inventor： Chua Swee Kwang ,  Chia Yong Poo

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L24/32 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/26145 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The package also includes a semiconductor die on the substrate in electrical communication with the contacts, and a die attach polymer attaching the die to the substrate. The die includes a recess, and the discrete component is contained in the recess encapsulated in the die attach polymer. A method for fabricating the package includes the steps of: attaching the discrete component to the substrate, placing the die attach polymer on the discrete component and the substrate, pressing the die into the die attach polymer to encapsulate the discrete component in the recess and attach the die to the substrate, and then placing the die in electrical communication with the discrete component. An electronic system includes the semiconductor package mounted to a system substrate.

Abstract translation: 半导体封装包括具有触点的基板和与触点电连通的基板上的分立元件。 封装还包括与触点电连通的衬底上的半导体管芯，以及将管芯附接到衬底的管芯附接聚合物。 模具包括凹部，并且分离的部件包含在封装在管芯附着聚合物中的凹部中。 一种用于制造封装的方法包括以下步骤：将分立组件附接到衬底上，将芯片连接聚合物放置在分立组件和衬底上，将模具压入芯片附着聚合物以将分离组件封装在凹槽中并附着 将裸片冲压到基板上，然后将模具放置在与分立元件电连通的位置。 电子系统包括安装到系统基板的半导体封装。

公开(公告)号：US20080237887A1

公开(公告)日：2008-10-02

申请号：US11693651

申请日：2007-03-29

Applicant: Hem Takiar ,  Shrikar Bhagath

Inventor： Hem Takiar ,  Shrikar Bhagath

IPC: H01L23/52

CPC classification number: H01L24/85 ,  H01L23/49575 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4845 ,  H01L2224/48465 ,  H01L2224/48479 ,  H01L2224/48482 ,  H01L2224/48499 ,  H01L2224/48599 ,  H01L2224/49175 ,  H01L2224/78302 ,  H01L2224/83855 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85986 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/48471 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device is disclosed including die bond pads which are heightened to allow wire bonding of offset stacked die even in tight offset configurations. After a first die is affixed to a substrate, one or more layers of an electrical conductor may be provided on some or all of the die bond pads of the first substrate to raise the height of the bond pads. The conductive layers may for example be conductive balls deposited on the die bond pads of the first substrate using a known wire bond capillary. Thereafter, a second die may be added, and wire bonding of the first die may be accomplished using a known wire bond capillary mounting a wire bond ball on a raised surface of a first semiconductor die bond pad.

Abstract translation: 公开了一种半导体器件，其包括芯片接合焊盘，其加强以允许偏移堆叠焊盘的引线接合，即使在紧密偏移配置中。 在将第一裸片固定到基底之后，可以在第一衬底的一些或全部芯片接合焊盘上提供一层或多层电导体，以提高焊盘的高度。 导电层可以例如是使用已知的引线键合毛细管沉积在第一衬底的管芯接合焊盘上的导电球。 此后，可以添加第二管芯，并且可以使用在第一半导体管芯接合焊盘的凸起表面上安装引线接合球的公知的引线接合毛细管来实现第一管芯的引线接合。

公开(公告)号：US20080132005A1

公开(公告)日：2008-06-05

申请号：US12015545

申请日：2008-01-17

Applicant: Mitsuru Kinoshita ,  Tsugihiko Hirano ,  Katsunori Takahashi

Inventor： Mitsuru Kinoshita ,  Tsugihiko Hirano ,  Katsunori Takahashi

IPC: H01L21/56

CPC classification number: C25D3/56 ,  C25D17/10 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01049

Abstract: An electroplating method calls for immersing a body to be plated in a plating solution containing tin and bismuth to form a tin-bismuth alloy skin layer on surfaces of the body. The plating is carried out such that a solid tin metal and a solid bismuth metal placed in the plating solution are connected to an anode and the body to be plated is connected to a cathode of a power supply.

Abstract translation: 电镀方法要求将要镀覆的物体浸入含有锡和铋的镀液中，以在主体的表面上形成锡 - 铋合金表皮层。 进行电镀，使得放置在电镀液中的固体锡金属和固体铋金属连接到阳极，并且待电镀的主体连接到电源的阴极。