公开(公告)号：US20150035005A1

公开(公告)日：2015-02-05

申请号：US13954826

申请日：2013-07-30

申请人： Anup Bhalla

发明人： Anup Bhalla

IPC分类号： H01L27/06 ,  H01L21/8248

CPC分类号： H01L27/0629 ,  H01L21/8248 ,  H01L23/4952 ,  H01L23/49562 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/423 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： This invention discloses a semiconductor power device formed in a semiconductor substrate. The semiconductor power device further includes a channel stop region near a peripheral of the semiconductor substrate wherein the channel stop region further includes a peripheral terminal of a diode corresponding with another terminal of the diode laterally opposite from the peripheral terminal disposed on an active area of the semiconductor power device. In an embodiment of this invention, the semiconductor power device is an insulated gate bipolar transistor (IGBT).

摘要翻译： 本发明公开了一种形成在半导体衬底中的半导体功率器件。 半导体功率器件还包括在半导体衬底的周边附近的通道停止区域，其中通道停止区域还包括二极管的外围端子，该二极管对应于二极管的另一个端子，该二极管的外部端子与设置在 半导体功率器件。 在本发明的一个实施例中，半导体功率器件是绝缘栅双极晶体管（IGBT）。

公开(公告)号：US08946942B2

公开(公告)日：2015-02-03

申请号：US12074327

申请日：2008-03-03

申请人： Sik K. Lui ,  Anup Bhalla

发明人： Sik K. Lui ,  Anup Bhalla

IPC分类号： H01H47/00 ,  H03K17/16 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01H49/00 ,  H01L29/0696 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/7803 ,  H01L29/7813 ,  H01L2924/0002 ,  H03K17/04123 ,  H03K17/08122 ,  H03K17/122 ,  H03K17/164 ,  H03K17/687 ,  Y10T29/49105 ,  Y10T307/747 ,  Y10T307/76 ,  H01L2924/00

摘要： This invention discloses a power switch that includes a fast-switch semiconductor power device and a slow-switch semiconductor power device controllable to turn on and off a current transmitting therethrough. The slow-switch semiconductor power device further includes a ballasting resistor for increasing a device robustness of the slow switch semiconductor power device. In an exemplary embodiment, the fast-switch semiconductor power device includes a fast switch metal oxide semiconductor field effect transistor (MOSFET) and the slow-switch semiconductor power device includes a slow switch MOSFET wherein the slow switch MOSFET further includes a source ballasting resistor.

公开(公告)号：US08933550B2

公开(公告)日：2015-01-13

申请号：US13442757

申请日：2012-04-09

申请人： Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

发明人： Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

IPC分类号： H01L23/22 ,  H01L29/40 ,  H01L23/495 ,  H01L23/00

CPC分类号： H01L23/49575 ,  H01L23/49562 ,  H01L23/49589 ,  H01L24/37 ,  H01L24/39 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/84

摘要： A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level.

摘要翻译： 用于功率转换器应用的半导体封装包括低边MOSFET芯片和高边MOSFET芯片。 半导体封装可以进一步包围电容器，而电容器可以是分立元件或芯片级与低边MOSFET的集成元件。 半导体封装还可以包括PIC芯片，以在半导体芯片组件封装级别上提供完整的功率转换器。

公开(公告)号：US20140332882A1

公开(公告)日：2014-11-13

申请号：US13892312

申请日：2013-05-13

申请人： SiK K. Lui ,  Anup Bhalla

发明人： SiK K. Lui ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7839 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/66143 ,  H01L29/66712 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872

摘要： A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.

摘要翻译： 一种用于制造肖特基二极管的方法，包括以下步骤：1）提供具有与第一导电类型相反的第二导电类型的掺杂剂的区域，以在所述第一导电类型的半导体衬底中形成顶部掺杂区域; 2）通过顶部掺杂区域提供沟槽至预定深度并提供第二导电类型的掺杂剂以形成第二导电类型的底部掺杂区域; 以及3）将至少从顶部掺杂区域的底部延伸到底部掺杂区域的顶部的沟槽的侧壁上的肖特基势垒金属层衬里。

公开(公告)号：US08884406B2

公开(公告)日：2014-11-11

申请号：US13231872

申请日：2011-09-13

申请人： Yingying Lou ,  Tiesheng Li ,  Yu Wang ,  Anup Bhalla

发明人： Yingying Lou ,  Tiesheng Li ,  Yu Wang ,  Anup Bhalla

IPC分类号： H01L21/312 ,  H01L29/66 ,  H01L21/66 ,  H01L29/40

CPC分类号： H01L22/12 ,  H01L29/407 ,  H01L29/66734 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device wafer includes a test structure. The test structure includes a layer of material having an angle-shaped test portion disposed on at least a portion of a surface of the semiconductor wafer. A ruler marking on the surface of the semiconductor wafer proximate the test portion is adapted to facilitate measurement of a change in length of the test portion.

摘要翻译： 半导体器件晶片包括测试结构。 测试结构包括具有设置在半导体晶片的表面的至少一部分上的角形测试部分的材料层。 在靠近测试部分的标记在半导体晶片的表面上的标尺适于便于测量测试部分的长度变化。

公开(公告)号：US08772144B2

公开(公告)日：2014-07-08

申请号：US13294903

申请日：2011-11-11

申请人： TingGang Zhu ,  Anup Bhalla ,  Ping Huang ,  Yueh-se Ho

发明人： TingGang Zhu ,  Anup Bhalla ,  Ping Huang ,  Yueh-se Ho

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L29/872 ,  H01L21/0217 ,  H01L21/0254 ,  H01L21/28581 ,  H01L21/30612 ,  H01L21/31111 ,  H01L21/56 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L25/18 ,  H01L27/0248 ,  H01L27/0814 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/405 ,  H01L29/417 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/861 ,  H01L29/8611 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05016 ,  H01L2224/05567 ,  H01L2224/11616 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction nitride-based Schottky diode is thus realized. In another embodiment, a protection circuit for a vertical GaN Schottky diode employs a silicon-based vertical PN junction diode connected in parallel to the GaN Schottky diode to divert reverse bias avalanche current.

摘要翻译： 使用绝缘基板形成垂直导电氮化物基肖特基二极管，绝缘基板在二极管器件用晶片级模塑料封装在前侧之后被提起。 晶片级成型复合体在二极管器件的前侧提供结构支撑，以允许绝缘基板被提起，使得可以在作为阴极的二极管器件的背面上形成导电层。 因此实现了基于垂直导电氮化物的肖特基二极管。 在另一个实施例中，用于垂直GaN肖特基二极管的保护电路采用与GaN肖特基二极管并联连接的硅基垂直PN结二极管，以转移反向偏置雪崩电流。

公开(公告)号：US20140167212A1

公开(公告)日：2014-06-19

申请号：US13712980

申请日：2012-12-13

申请人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

发明人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

IPC分类号： H01L21/762 ,  H01L29/06

CPC分类号： H01L29/407 ,  H01L21/76205 ,  H01L29/04 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.

摘要翻译： 公开了具有多个嵌入式电位扩展电容结构（TSMEC）和方法的端接结构，用于在具有底部漏电极的体半导体层（BSL）的顶部端接邻近的沟槽MOSFET。 BSL具有支持漏极 - 源极电压（DSV）的近端体半导体壁（PBSW），并将TSMEC与沟槽MOSFET分离。 TSMEC具有由PBSW和远端体半导体壁（DBSW）界定的氧化物填充的大深沟槽（OFLDT）。 OFLDT包括位于大深度氧化物沟槽内部以及PBSW和DBSW之间的BSL中的大型深层氧化物沟槽和嵌入式电容结构（EBCS），用于在其间空间扩展DSV。 在一个实施例中，EBCS包含OFLDT的交错导电嵌入式多晶半导体区域（EPSR）和氧化物柱（OXC），与PBSW相邻的近端EPSR连接到活动上部源区域，并且与DBSW相邻的远端EPSR被连接到 星展集团

公开(公告)号：US08698196B2

公开(公告)日：2014-04-15

申请号：US13170965

申请日：2011-06-28

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

IPC分类号： H01L29/66 ,  H01L29/06

CPC分类号： H01L29/66113 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/822 ,  H01L27/0248 ,  H01L27/0255

摘要： A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.

公开(公告)号：US08643135B2

公开(公告)日：2014-02-04

申请号：US13134163

申请日：2011-05-31

申请人： Madhur Bobde ,  Sik K Lui ,  Anup Bhalla

发明人： Madhur Bobde ,  Sik K Lui ,  Anup Bhalla

IPC分类号： H01L23/58 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/407 ,  H01L29/0661 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein the edge termination area comprises a wide trench filled with a field-crowding reduction filler and a buried field plate buried under a top surface of the semiconductor substrate and laterally extended over a top portion of the field crowding field to move a peak electric field laterally away from the active cell area. In a specific embodiment, the field-crowding reduction filler comprises a silicon oxide filled in the wide trench.

摘要翻译： 本发明公开了一种半导体功率器件，其设置在半导体衬底中并且具有有源电池区域和边缘终止区域，其中边缘终端区域包括填充有场强拥挤减少填充物的宽沟槽和埋在顶表面下方的掩埋场板 并且横向延伸超过场域拥挤场的顶部以使峰值电场横向移动到有源电池区域。 在一个具体的实施例中，场地拥挤减少填料包括填充在宽沟槽中的氧化硅。

公开(公告)号：US20130277740A1

公开(公告)日：2013-10-24

申请号：US13923065

申请日：2013-06-20

申请人： Lingpeng Guan ,  Anup Bhalla ,  Tinggang Zhu ,  Madhur Bobde

发明人： Lingpeng Guan ,  Anup Bhalla ,  Tinggang Zhu ,  Madhur Bobde

IPC分类号： H01L29/78

CPC分类号： H01L29/7823 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/47 ,  H01L29/7811

摘要： A superjunction device and methods for layout design and fabrication of a superjunction device are disclosed. A layout of active cell column structures can be configured so that a charge due to first conductivity type dopants balances out charge due to second conductivity type dopants in a doped layer in an active cell region. A layout of end portions of the active cell column structures proximate termination column structures can be configured so that a charge due to the first conductivity type dopants in the end portions and a charge due to the first conductivity type dopants in the termination column structures balances out charge due to the second conductivity type dopants in a portion of the doped layer between the termination column structures and the end portions.

摘要翻译： 公开了一种用于布置设计和超级结装置制造的超结装置和方法。 可以配置活性单元列结构的布局，使得由于第一导电型掺杂剂引起的电荷由于活性单元区域中的掺杂层中的第二导电类型掺杂物而平衡电荷。 靠近端子列结构的活性单元列结构的端部的布局可以被配置为使得由于端部中的第一导电类型掺杂物引起的电荷和由端接塔结构中的第一导电类型掺杂剂引起的电荷平衡 在终端柱结构和端部之间的掺杂层的一部分中的第二导电类型掺杂剂引起的电荷。