公开(公告)号：US5402715A

公开(公告)日：1995-04-04

申请号：US277472

申请日：1994-07-19

申请人： Masayasu Kurachi ,  Seiichi Kondo

发明人： Masayasu Kurachi ,  Seiichi Kondo

IPC分类号： A21C3/02 ,  A21C11/06 ,  A23L7/109 ,  A21C3/10 ,  A21C11/22 ,  A21C11/24 ,  A23P1/00

CPC分类号： A21C11/06 ,  A23L7/109

摘要： A rolling mill for use in a noodle making apparatus, of the type adapted for rolling a noodle sheet of a predetermined width, includes a plurality of rolling sections arranged in a set and each having pairs of upper and lower rolls. The set includes a pair of grooved rolls for pressingly forming a plurality of mountain and valley portions on the noodle sheet parallel to the extending longitudinal direction thereof, and at least one pair of gear-type rolls for pressingly forming a plurality of mountain and valley portions on the noodle sheet parallel to the transverse direction thereof.

摘要翻译： 一种用于轧制预定宽度的面条的面条制造装置的轧机，包括多个设置成一组上下辊的轧制部。 该组件包括一对用于在平面于其延伸的纵向方向上在面条上压制形成多个山谷部分的凹槽辊，以及至少一对齿轮型辊，用于按压形成多个山谷部分 在平行于其横向的面条上。

公开(公告)号：US5013526A

公开(公告)日：1991-05-07

申请号：US438596

申请日：1989-11-17

申请人： Nobuyoshi Kobayashi ,  Masayuki Suzuki ,  Seiichi Kondo ,  Makoto Matsui ,  Kiichiro Mukai

发明人： Nobuyoshi Kobayashi ,  Masayuki Suzuki ,  Seiichi Kondo ,  Makoto Matsui ,  Kiichiro Mukai

IPC分类号： C23C14/14 ,  C23C16/06 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/532 ,  H01L39/06 ,  H01L39/12

CPC分类号： H01L23/53285 ,  H01L39/12 ,  H01L2924/0002 ,  Y10S420/901 ,  Y10T428/12528 ,  Y10T428/12806

摘要： A superconducting material made of tungsten or molybdenum containing a specified amount of silicon, a wiring made of this superconducting material, and a semiconductor device using this wiring.The above-mentioned superconducting material undegoes no damage even in the steps of heat treatments effected after the formation of a wiring therefrom by virtue of its high melting point, and can be very easily patterned by reactive ion etching using SF.sub.6 as an etching gas, which has heretofore been generally employed. These features, in which conventional superconducting materials are lacking, allow the superconducting material of the present invention to exhibit excellent properties particularly when used in the wirings of a semiconductor device.

公开(公告)号：US10769268B2

公开(公告)日：2020-09-08

申请号：US15696569

申请日：2017-09-06

申请人： Ryutaro Sakanashi ,  Yuuichiroh Hayashi ,  Yasuharu Fukuda ,  Seiichi Kondo ,  Taichi Watanabe

发明人： Ryutaro Sakanashi ,  Yuuichiroh Hayashi ,  Yasuharu Fukuda ,  Seiichi Kondo ,  Taichi Watanabe

IPC分类号： G06F21/44 ,  G06F21/60 ,  H04L29/06

摘要： There is provided an information processing device in which an application of an electronic device provides a service to a user, the information processing device including a processor; and a memory that includes instructions, which when executed, cause the processor to execute the following steps: associating the application with a processing flow; associating the processing flow with a scope of authorization of an external service; retrieving the scope of the authorization of the external service required by the processing flow associated with the application; retrieving authorized information representing a scope of authorization of the external service authorized by the user; and providing, for each external service, information indicating whether the external service is authorized, based on a result of comparing the scope of the authorization of the external service required by the processing flow with the scope of the authorization of the external service authorized by the user.

公开(公告)号：US20050064699A1

公开(公告)日：2005-03-24

申请号：US10940820

申请日：2004-09-15

申请人： Seiichi Kondo ,  Kaori Misawa ,  Shunichi Tokitoh ,  Takashi Nasuno

发明人： Seiichi Kondo ,  Kaori Misawa ,  Shunichi Tokitoh ,  Takashi Nasuno

IPC分类号： H01L27/00 ,  H01L21/28 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76826 ,  H01L21/02126 ,  H01L21/02137 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3124 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/318 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835

摘要： A first CVD dielectric layer is deposited on a surface of a semiconductor substrate. Next, low-k layers are deposited in at least two different steps to form one of a via-layer dielectric film and a wiring-layer dielectric film on the first CVD dielectric layer. Immediately after the depositions, thermal treatment is performed. A second CVD dielectric layer is deposited on the low-k layers. A groove is formed in the second CVD dielectric layer and the low-k layers. A metal layer is deposited on that structure, filling the groove. The metal layer is removed from the second CVD dielectric layer by chemical mechanical polishing.

摘要翻译： 第一CVD绝缘层沉积在半导体衬底的表面上。 接下来，在至少两个不同的步骤中沉积低k层，以在第一CVD电介质层上形成通孔层电介质膜和布线层电介质膜之一。 沉积后立即进行热处理。 在低k层上沉积第二CVD介电层。 在第二CVD介质层和低k层中形成凹槽。 在该结构上沉积金属层，填充凹槽。 金属层通过化学机械抛光从第二CVD介电层去除。

公开(公告)号：US06849542B2

公开(公告)日：2005-02-01

申请号：US10272831

申请日：2002-10-18

申请人： Soichi Katagiri ,  Ui Yamaguchi ,  Seiichi Kondo ,  Kan Yasui ,  Masahiro Kaise ,  Minoru Honda

发明人： Soichi Katagiri ,  Ui Yamaguchi ,  Seiichi Kondo ,  Kan Yasui ,  Masahiro Kaise ,  Minoru Honda

IPC分类号： B24B57/02 ,  B24D3/32 ,  B24D3/34 ,  B24D7/06 ,  H01L21/304 ,  H01L21/321 ,  H01L21/463

CPC分类号： B24B37/245 ,  B24B37/042 ,  B24B37/22 ,  B24B57/02 ,  B24D3/32 ,  B24D3/344 ,  B24D7/063 ,  H01L21/3212

摘要： The invention provides a method for manufacturing a semiconductor device with reduced dishing and erosion. In this method for manufacturing a semiconductor device, the convex/concave pattern is planarized by relatively moving a substrate having the convex/concave pattern on the surface and a polishing tool with pressing the convex/concave surface of the substrate on the polishing tool. The polishing tool is provided with a grindstone 10 having a plurality of polygonal segments 20, which comprises abrasive 23 that is bonded together with resin 24 and contains pores 22. The polygonal segments are arranged so that corners of three or more polygonal segments are not located near each other.

摘要翻译： 本发明提供一种制造具有减少的凹陷和侵蚀的半导体器件的方法。 在这种制造半导体器件的方法中，通过在表面上相对移动具有凸/凹图案的衬底和将抛光工具上的衬底的凸/凹表面压在一起的抛光工具，使凸/凹图案平坦化。 抛光工具设置有具有多个多边形节段20的磨石10，磨石10包括与树脂24结合并包含孔22的磨料23。多边形节段被布置成使得三个或更多个多边形节段的角部不位于 靠近对方

公开(公告)号：US06734103B2

公开(公告)日：2004-05-11

申请号：US10081212

申请日：2002-02-25

申请人： Souichi Katagiri ,  Ui Yamaguchi ,  Seiichi Kondo ,  Kan Yasui ,  Yoshio Kawamura

发明人： Souichi Katagiri ,  Ui Yamaguchi ,  Seiichi Kondo ,  Kan Yasui ,  Yoshio Kawamura

IPC分类号： H01L21302

CPC分类号： B24B7/228 ,  B24B53/02 ,  C23F3/00 ,  H01L21/3212 ,  H01L21/7684

摘要： A method of manufacturing is described wherein a semiconductor device has a substrate as workpiece with an insulation film formed on the substrate, openings formed inside the insulation film, a first conductive film is formed inside the openings and on a surface of the insulation film, a second conductive film is formed on the first conductive film, and the first and the second conductive films are formed inside openings by planarizing a surface of second conductive film and a surface part of the first conductive film with a fixed abrasive tool. The method includes supplying a first processing liquid, planarizing the surface of the second conductive film with the first processing liquid and the fixed abrasive tool, switching the supply of liquid from a first processing liquid to a second processing liquid, and planarizing the surface of second conductive film and the surface of part of the first conductive film with the second processing liquid and the fixed abrasive tool.

摘要翻译： 描述了一种制造方法，其中半导体器件具有作为工件的基板，在基板上形成绝缘膜，形成在绝缘膜内部的开口，第一导电膜形成在开口内部和绝缘膜的表面上， 第二导电膜形成在第一导电膜上，并且通过用固定的研磨工具平面化第二导电膜的表面和第一导电膜的表面部分，在开口内形成第一和第二导电膜。 该方法包括提供第一处理液体，将第二导电膜的表面与第一处理液体和固定研磨工具平坦化，将液体从第一处理液体切换到第二处理液体，并将第二处理液体的表面平坦化 导电膜和第一导电膜的部分表面与第二处理液和固定研磨工具。

公开(公告)号：US06525336B1

公开(公告)日：2003-02-25

申请号：US08463761

申请日：1995-06-05

申请人： Seiichi Kondo ,  Yasuo Wada ,  Tsuyoshi Uda ,  Tokuo Kure ,  Tsuneo Ichiguchi ,  Shinji Okazaki ,  Yoshimasa Murayama

发明人： Seiichi Kondo ,  Yasuo Wada ,  Tsuyoshi Uda ,  Tokuo Kure ,  Tsuneo Ichiguchi ,  Shinji Okazaki ,  Yoshimasa Murayama

IPC分类号： H01L2906

CPC分类号： G11C13/025 ,  B82Y10/00 ,  B82Y15/00 ,  G11C11/34 ,  G11C19/00 ,  G11C2216/08 ,  H01L49/006 ,  H03K19/02

摘要： A superfine electronic device is disclosed, which is constructed by atomic fine lines having a structure in which a plurality of atoms are arranged on one or a plurality of straight lines, in a ring shape or on curves with a size of atomic level, and which includes elements for doping electrons and holes. Using these atomic fine lines, it is possible to integrate semiconductor elements utilizing pn junctions at an atomic level with a high density. A groove having a sufficiently small size is formed in an insulating film disposed on a substrate. Then, atoms or molecules are supplied on the substrate and in the groove, which and are heated to a temperature sufficiently high for moving the atoms or molecules during or after the supply thereof to form a quantum fine line at edge portions of the groove.

摘要翻译： 公开了一种超细电子器件，其由具有多个原子排列在一个或多个直线上的原子细线构成，具有环形或具有原子级尺寸的曲线，并且其中 包括用于掺杂电子和空穴的元件。 使用这些原子细线，可以利用高密度的原子级的pn结集成半导体元件。 在设置在基板上的绝缘膜中形成具有足够小尺寸的凹槽。 然后，原子或分子被提供在衬底和沟槽中，并且被加热到足够高的温度以在其供给期间或之后移动原子或分子，以在槽的边缘部分处形成量子细线。

公开(公告)号：US5561300A

公开(公告)日：1996-10-01

申请号：US994968

申请日：1992-12-22

申请人： Yasuo Wada ,  Seiichi Kondo ,  Tsuyoshi Uda ,  Masukazu Igarashi ,  Hiroshi Kajiyama ,  Hisashi Nagano ,  Akito Sakurai ,  Tsuneo Ichiguchi

发明人： Yasuo Wada ,  Seiichi Kondo ,  Tsuyoshi Uda ,  Masukazu Igarashi ,  Hiroshi Kajiyama ,  Hisashi Nagano ,  Akito Sakurai ,  Tsuneo Ichiguchi

IPC分类号： G01Q90/00 ,  G11B9/00 ,  G11C11/34 ,  G11C13/00 ,  G11C19/00 ,  H01L27/06 ,  H01L27/085 ,  H01L49/00 ,  H03F3/04 ,  H03K17/51 ,  H03K17/54 ,  H03K17/56 ,  H03K19/02 ,  H03K19/08 ,  H01J37/30 ,  H02B1/24

CPC分类号： B82Y15/00 ,  B82Y10/00 ,  G11B9/14 ,  G11B9/1463 ,  G11C11/34 ,  G11C13/00 ,  G11C19/00 ,  H01L27/06 ,  H01L27/085 ,  H01L49/00 ,  H01L49/006 ,  H03F3/04 ,  H03K17/51 ,  H03K17/545 ,  H03K17/56 ,  H03K19/02 ,  H03K19/08 ,  G11C13/025 ,  G11C2213/81 ,  G11C2216/08 ,  Y10S977/94 ,  Y10T307/74 ,  Y10T307/937

摘要： In an atomic switch, opposite ends of an atom wire are connected to an input and output, and a switching gate is connected to a switching power supply. An input signal is outputted when a switching atom is connected to the atom wire, whereas an input signal is not outputted when the switching atom is moved to disconnect from the atom wire. There are provided an atom wire having a plurality of atoms arranged in a line or in a plurality of lines, in a ring shape, or in a curved line, and a switching gate made of an atom wire. The atom wire is switched by the field effect of the switching gate.

摘要翻译： 在原子开关中，原子线的相对端连接到输入和输出，并且开关栅极连接到开关电源。 当切换原子连接到原子线时输出输入信号，而当切换原子移动以与原子线分离时，输出信号不输出。 提供一种原子线，其具有以线状或多条排列成环状或曲线的多个原子以及由原子线构成的开关栅极。 原子线由开关栅极的场效应切换。

公开(公告)号：US5510614A

公开(公告)日：1996-04-23

申请号：US184068

申请日：1994-01-21

申请人： Munehisa Mitsuya ,  Yasuo Wada ,  Seiji Heike ,  Seiichi Kondo

发明人： Munehisa Mitsuya ,  Yasuo Wada ,  Seiji Heike ,  Seiichi Kondo

IPC分类号： C04B41/00 ,  C04B41/80 ,  C23C26/00 ,  G01Q30/02 ,  G01Q60/10 ,  G11B9/00 ,  H01J37/00

CPC分类号： G01Q30/02 ,  B82Y35/00 ,  C04B41/0027 ,  C04B41/0045 ,  C04B41/009 ,  C04B41/80 ,  C23C26/00 ,  G01Q60/10 ,  B82Y10/00 ,  C04B2111/94 ,  G11B9/14 ,  G11B9/149 ,  H01J2237/31732 ,  Y10S977/855

摘要： A surface of an insulator or semiconductor substrate is irradiated with a beam such as an electron beam, an electromagnetic wave beam, an ion beam, etc. to excite carriers so as to form an electrical conductive layer on the surface of and in the inside of the substrate to thereby make it possible to perform observation and micro working on the insulator by using a scanning tunneling microscope.

摘要翻译： 用电子束，电磁波束，离子束等光束照射绝缘体或半导体基板的表面，以激励载流子，以在其表面上和内部形成导电层 从而能够通过使用扫描隧道显微镜对绝缘体进行观察和微加工。