公开(公告)号：US20050014365A1

公开(公告)日：2005-01-20

申请号：US10881231

申请日：2004-06-30

Applicant: Kwang-Jin Moon ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Hyun-Su Kim

Inventor： Kwang-Jin Moon ,  Gil-Heyun Choi ,  Sang-Bom Kang ,  Hyun-Su Kim

IPC: H01L21/24 ,  C23C16/16 ,  C23C16/18 ,  C23C16/56 ,  H01L21/285 ,  H01L21/4763 ,  H01L21/768

CPC classification number: C23C16/56 ,  C23C16/16 ,  C23C16/18 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76855

Abstract: The present invention provides methods of forming cobalt layers on a structure comprising forming a preliminary cobalt layer on a semiconductor substrate by introducing an organic metal precursor onto the semiconductor substrate and treating a surface of the preliminary cobalt layer under an atmosphere of a hydrogen-containing gas to remove impurities contained in the preliminary cobalt layer. Compositions of cobalt layers are also provided. Further provided are semiconductor devices comprising cobalt layers provided herein.

Abstract translation: 本发明提供了在包括在半导体衬底上形成初步钴层的结构上形成钴层的方法，该方法是在有机金属前体引入到半导体衬底上并在含氢气体气氛下处理预钴层的表面 以除去预备钴层中所含的杂质。 还提供了钴层的组成。 还提供了包括本文提供的钴层的半导体器件。

公开(公告)号：US09691684B2

公开(公告)日：2017-06-27

申请号：US14327558

申请日：2014-07-09

Applicant: Jae-hwa Park ,  Sung-hee Kang ,  Kwang-jin Moon ,  Byung-lyul Park ,  Suk-chul Bang

Inventor： Jae-hwa Park ,  Sung-hee Kang ,  Kwang-jin Moon ,  Byung-lyul Park ,  Suk-chul Bang

IPC: H01L27/108 ,  H01L23/48 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L28/90 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: An integrated circuit device is provided which includes a through-silicon via (TSV) structure and one or more decoupling capacitors, along with a method of manufacturing the same. The integrated circuit device may include a semiconductor structure including a semiconductor substrate, a TSV structure passing through the semiconductor substrate, and a decoupling capacitor formed in the semiconductor substrate and connected to the TSV structure. The TSV structure and the one or more decoupling capacitors may be substantially simultaneously formed. A plurality of decoupling capacitors may be disposed within a keep out zone (KOZ) of the TSV structure. The plurality of decoupling capacitors may have the same or different widths and/or depths. An isopotential conductive layer may be formed to reduce or eliminate a potential difference between different parts of the TSV structure.

公开(公告)号：US09379042B2

公开(公告)日：2016-06-28

申请号：US14504647

申请日：2014-10-02

Applicant: Jae-Hwa Park ,  Suk-Chul Bang ,  Byung-Lyul Park ,  Kwang-Jin Moon

Inventor： Jae-Hwa Park ,  Suk-Chul Bang ,  Byung-Lyul Park ,  Kwang-Jin Moon

IPC: H01L21/02 ,  H01L23/48 ,  H01L49/02 ,  H01L21/768 ,  H01L27/108 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/5384 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a capacitor including an electrode formed in a first area on a substrate; a through-silicon-via (TSV) landing pad formed in a second area on the substrate, the TSV landing pad including the same material as the electrode; a multi-layered interconnection structure formed on the capacitor and the TSV landing pad; and a TSV structure passing through the substrate, the TSV structure being connected to the multi-layered interconnection structure through the TSV landing pad.

Abstract translation: 提供集成电路装置。 集成电路装置包括：电容器，包括形成在基板上的第一区域中的电极; 形成在所述基板上的第二区域中的通硅通孔（TSV）着陆焊盘，所述TSV着陆焊盘包括与所述电极相同的材料; 形成在电容器和TSV着陆板上的多层互连结构; TSV结构通过基板，TSV结构通过TSV着陆焊盘连接到多层互连结构。

公开(公告)号：US09142490B2

公开(公告)日：2015-09-22

申请号：US14325335

申请日：2014-07-07

Applicant: Jae-hwa Park ,  Kwang-jin Moon ,  Byung-lyul Park ,  Suk-chul Bang

Inventor： Jae-hwa Park ,  Kwang-jin Moon ,  Byung-lyul Park ,  Suk-chul Bang

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/53295 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Provided is an integrated circuit device including a through-silicon-via (TSV) structure and a method of manufacturing the integrated circuit device. The integrated circuit device includes a semiconductor structure including a substrate and an interlayer insulating film, a TSV structure passing through the substrate and the interlayer insulating film, a via insulating film substantially surrounding the TSV structure, and an insulating spacer disposed between the interlayer insulating film and the via insulating film.

Abstract translation: 提供了一种包括贯穿硅通孔（TSV）结构的集成电路器件以及集成电路器件的制造方法。 集成电路装置包括：半导体结构，包括基板和层间绝缘膜，通过基板的TSV结构和层间绝缘膜，基本上包围TSV结构的通孔绝缘膜，以及设置在层间绝缘膜 和通孔绝缘膜。

公开(公告)号：US09018768B2

公开(公告)日：2015-04-28

申请号：US13627790

申请日：2012-09-26

Applicant: Byung-lyul Park ,  Gil-heyun Choi ,  Suk-chul Bang ,  Kwang-jin Moon ,  Dong-chan Lim ,  Deok-young Jung

Inventor： Byung-lyul Park ,  Gil-heyun Choi ,  Suk-chul Bang ,  Kwang-jin Moon ,  Dong-chan Lim ,  Deok-young Jung

IPC: H01L23/48 ,  H01L23/02 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L21/76898 ,  H01L21/76801 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565

Abstract: A semiconductor device includes a circuit pattern over a first surface of a substrate, an insulating interlayer covering the circuit pattern, a TSV structure filling a via hole through the insulating interlayer and the substrate, an insulation layer structure on an inner wall of the via hole and on a top surface of the insulating interlayer, a buffer layer on the TSV structure and the insulation layer structure, a conductive structure through the insulation layer structure and a portion of the insulating interlayer to be electrically connected to the circuit pattern, a contact pad onto a bottom of the TSV structure, and a protective layer structure on a second surface the substrate to surround the contact pad.

Abstract translation: 半导体器件包括在衬底的第一表面上的电路图案，覆盖电路图案的绝缘夹层，填充通过绝缘夹层和衬底的通孔的TSV结构，在通孔的内壁上的绝缘层结构 并且在绝缘中间层的上表面上，具有TSV结构和绝缘层结构的缓冲层，通过绝缘层结构的导电结构和电连接到电路图案的绝缘夹层的一部分，接触垫 到TSV结构的底部，以及在第二表面上的保护层结构，以包围接触垫。

公开(公告)号：US20150108605A1

公开(公告)日：2015-04-23

申请号：US14504647

申请日：2014-10-02

Applicant: Jae-Hwa Park ,  Suk-Chul Bang ,  Byung-Lyul Park ,  Kwang-Jin Moon

Inventor： Jae-Hwa Park ,  Suk-Chul Bang ,  Byung-Lyul Park ,  Kwang-Jin Moon

IPC: H01L23/50 ,  H01L49/02 ,  H01L27/108 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/5384 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a capacitor including an electrode formed in a first area on a substrate; a through-silicon-via (TSV) landing pad formed in a second area on the substrate, the TSV landing pad including the same material as the electrode; a multi-layered interconnection structure formed on the capacitor and the TSV landing pad; and a TSV structure passing through the substrate, the TSV structure being connected to the multi-layered interconnection structure through the TSV landing pad.

Abstract translation: 提供集成电路装置。 集成电路装置包括：电容器，包括形成在基板上的第一区域中的电极; 形成在所述基板上的第二区域中的通硅通孔（TSV）着陆焊盘，所述TSV着陆焊盘包括与所述电极相同的材料; 形成在电容器和TSV着陆板上的多层互连结构; TSV结构通过基板，TSV结构通过TSV着陆焊盘连接到多层互连结构。

公开(公告)号：US20150102497A1

公开(公告)日：2015-04-16

申请号：US14506930

申请日：2014-10-06

Applicant: Jae-Hwa Park ,  Kwang-jin Moon ,  Suk-Chul Bang ,  Byung-Iyul Park ,  Jeong-gi Jin ,  Tae-seong Kim ,  Sung-hee Kang

Inventor： Jae-Hwa Park ,  Kwang-jin Moon ,  Suk-Chul Bang ,  Byung-Iyul Park ,  Jeong-gi Jin ,  Tae-seong Kim ,  Sung-hee Kang

IPC: H01L23/48 ,  H01L23/50 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/485 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/14511 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/00

Abstract: Integrated circuit (IC) devices are provided including: a first multi-layer wiring structure including a plurality of first wiring layers in a first region of a substrate at different levels and spaced apart from one another, and a plurality of first contact plugs between the plurality of first wiring layers and connected to the plurality of first wiring layers; a through-silicon via (TSV) landing pad including a first pad layer in a second region of the substrate at a same level as that of at least one first wiring layer from among the plurality of first wiring layers, and a second pad layer at a same level as that of at least one first contact plug from among the plurality of first contact plugs and contacts the first pad layer; a second multi-layer wiring structure on the TSV landing pad; and a TSV structure that passes through the substrate and is connected to the second multi-layer wiring structure through the TSV landing pad.

Abstract translation: 提供集成电路（IC）装置，包括：第一多层布线结构，其包括在不同层级并彼此间隔开的基板的第一区域中的多个第一布线层，以及多个第一接触塞 多个第一布线层并连接到多个第一布线层; 贯穿硅通孔（TSV）着陆焊盘，其包括在与所述多个第一布线层中的至少一个第一布线层相同水平的所述基板的第二区域中的第一焊盘层;以及第二焊盘层， 与所述多个第一接触插塞中的至少一个第一接触插塞的水平相同，并接触所述第一衬垫层; TSV着陆板上的第二层多层布线结构; 以及TSV结构，其通过所述基板，并且通过所述TSV着陆焊盘与所述第二多层布线结构连接。

公开(公告)号：US20150102395A1

公开(公告)日：2015-04-16

申请号：US14511801

申请日：2014-10-10

Applicant: Jae-Hwa Park ,  Kwang-Jin Moon ,  Byung-Lyul Park

Inventor： Jae-Hwa Park ,  Kwang-Jin Moon ,  Byung-Lyul Park

IPC: H01L27/108 ,  H01L23/64 ,  H01L49/02 ,  H01L23/48 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L23/481 ,  H01L23/642 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66181 ,  H01L29/945 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81469 ,  H01L2224/81481 ,  H01L2224/81484 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/014

Abstract: An integrated circuit device includes a semiconductor substrate having first and second semiconductor regions therein, a gate trench in the first semiconductor region and a gate electrode in the gate trench. The gate electrode has an upper surface below a surface of the semiconductor substrate. A semiconductor well region is provided in the second semiconductor region. A capacitor trench extends in the semiconductor well region and an upper capacitor electrode extends in the capacitor trench. An electrical interconnect (e.g., conductive plug) is provided, which is electrically connected to the upper capacitor electrode at an interface therebetween. This interface has an upper surface below the surface of the semiconductor substrate.

Abstract translation: 集成电路器件包括其中具有第一和第二半导体区域的半导体衬底，第一半导体区域中的栅极沟槽和栅极沟槽中的栅电极。 栅电极在半导体衬底的表面下方具有上表面。 半导体阱区域设置在第二半导体区域中。 电容器沟槽在半导体阱区域中延伸，并且上电容器电极在电容器沟槽中延伸。 提供电互连（例如，导电插头），其在它们之间的界面处电连接到上电容器电极。 该界面在半导体衬底的表面下方具有上表面。

公开(公告)号：US20120153500A1

公开(公告)日：2012-06-21

申请号：US13314575

申请日：2011-12-08

Applicant: Kyoung-Hee KIM ,  Gil-Heyun CHOI ,  Kyu-Hee HAN ,  Byung-Lyul PARK ,  Byung-Hee KIM ,  Sang-Hoon AHN ,  Kwang-Jin MOON

Inventor： Kyoung-Hee KIM ,  Gil-Heyun CHOI ,  Kyu-Hee HAN ,  Byung-Lyul PARK ,  Byung-Hee KIM ,  Sang-Hoon AHN ,  Kwang-Jin MOON

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/01327 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor device comprises a top surface having a first contact, a bottom surface having a second contact, a via hole penetrating a substrate, an insulation layer structure on a sidewall of the via hole, the insulation layer structure having an air gap therein, a through electrode having an upper surface and a lower surface on the insulation layer structure, the through electrode filling the via hole and the lower surface being the second contact, and a metal wiring electrically connected to the upper surface of the through electrode and electrically connected to the first contact.

Abstract translation: 半导体器件包括具有第一触点的顶表面，具有第二触点的底表面，穿透基板的通孔，在通孔的侧壁上的绝缘层结构，其中具有气隙的绝缘层结构， 所述贯通电极在所述绝缘层结构上具有上表面和下表面，所述贯通电极填充所述通孔，所述下表面是所述第二接触，以及金属布线，电连接到所述通孔的上表面，并电连接到 第一次接触。

公开(公告)号：US20120142185A1

公开(公告)日：2012-06-07

申请号：US13240040

申请日：2011-09-22

Applicant: Byung-Lyul Park ,  Gil-Heyun Choi ,  Suk-Chul Bang ,  Kwang-Jin Moon ,  Dong-Chan Lim ,  Deok-Young Jung

Inventor： Byung-Lyul Park ,  Gil-Heyun Choi ,  Suk-Chul Bang ,  Kwang-Jin Moon ,  Dong-Chan Lim ,  Deok-Young Jung

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05018 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05609 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In methods of manufacturing a semiconductor device, a substrate having a first surface and a second surface opposite to the first surface is prepared. A sacrificial layer pattern is formed in a region of the substrate that a through electrode will be formed. The sacrificial layer pattern extends from the first surface of the substrate in a thickness direction of the substrate. An upper wiring layer is formed on the first surface of the substrate. The upper wiring layer includes a wiring on the sacrificial layer pattern. The second surface of the substrate is partially removed to expose the sacrificial layer pattern. The sacrificial layer pattern is removed from the second surface of the substrate to form an opening that exposes the wiring. A through electrode is formed in the opening to be electrically connected to the wiring.

Abstract translation: 在制造半导体器件的方法中，制备具有与第一表面相对的第一表面和第二表面的衬底。 在基板的形成有通孔的区域中形成牺牲层图案。 牺牲层图案在基板的厚度方向上从基板的第一表面延伸。 在衬底的第一表面上形成上部布线层。 上部布线层包括在牺牲层图案上的布线。 部分去除衬底的第二表面以暴露牺牲层图案。 牺牲层图案从基板的第二表面移除以形成露出布线的开口。 通孔形成在开口中以与布线电连接。