公开(公告)号：US20120175635A1

公开(公告)日：2012-07-12

申请号：US13275151

申请日：2011-10-17

Applicant: Rolf Weis ,  Franz Hirler ,  Matthias Stecher ,  Armin Willmeroth ,  Gerald Deboy ,  Martin Feldtkeller

Inventor： Rolf Weis ,  Franz Hirler ,  Matthias Stecher ,  Armin Willmeroth ,  Gerald Deboy ,  Martin Feldtkeller

IPC: H01L27/06 ,  H01L29/778 ,  H01L29/788 ,  H01L29/20 ,  H01L29/161 ,  H01L27/088 ,  H01L27/098

CPC classification number: H01L27/0207 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/098 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H03K17/06

Abstract: A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract translation: 半导体器件布置包括具有负载路径的第一半导体器件和多个第二晶体管，每个具有第一和第二负载端子与控制端子之间的负载路径。 第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接。 每个第二晶体管的控制端连接到其它第二晶体管的负载端子。 第二晶体管中的一个具有其控制端子连接到第一半导体器件的负载端子之一。

公开(公告)号：US08188592B2

公开(公告)日：2012-05-29

申请号：US13228153

申请日：2011-09-08

Applicant: Peter Nelle ,  Matthias Stecher

Inventor： Peter Nelle ,  Matthias Stecher

IPC: H01L21/00

CPC classification number: H01L24/29 ,  H01L23/49513 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/05599 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32245 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/00014 ,  H01L2924/3512

Abstract: An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a heat sink plate and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the heat sink plate. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.

Abstract translation: 公开了一种配置成降低热应力的装置和方法。 一个实施例提供半导体芯片，散热板和层结构。 该层结构至少包括扩散焊料层和缓冲层。 层结构布置在半导体芯片和散热板之间。 缓冲层包括与扩散焊料层的材料相比柔软的材料，并且包括使得在温度范围内的温度波动期间半导体芯片中的热应力保持在预定值以下的层厚度。

公开(公告)号：US20110309441A1

公开(公告)日：2011-12-22

申请号：US12819856

申请日：2010-06-21

Applicant: Matthias Stecher ,  Hans Weber ,  Lincoln O'Riain ,  Birgit von Ehrenwall

Inventor： Matthias Stecher ,  Hans Weber ,  Lincoln O'Riain ,  Birgit von Ehrenwall

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/76

CPC classification number: H01L27/1207 ,  H01L21/187 ,  H01L21/743 ,  H01L21/76283 ,  H01L27/0251 ,  H01L27/1203 ,  H01L29/04 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/66681 ,  H01L29/7816

Abstract: An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided.

Abstract translation: 提供集成半导体器件。 集成半导体器件具有第二导电类型的第一半导体区域，与第一半导体区域形成pn结的第一导电类型的第二半导体区域，布置在第二导电类型的第二导电类型的非单晶半导体层 半导体区域，布置在非单晶半导体层上的第一导电类型的第一阱和至少一个第二阱以及使第一阱与至少一个第二阱和非单晶半导体层绝缘的绝缘结构。 此外，提供了一种用于形成半导体器件的方法。

公开(公告)号：US20110274129A1

公开(公告)日：2011-11-10

申请号：US12998968

申请日：2009-12-02

Applicant: Peter Bauer ,  Karsten Braeuer ,  Marco Flach ,  Andreas Langner ,  Richard Schmidt ,  Clemens Schmitt ,  Gerhard Schoetz ,  Matthias Stecher

Inventor： Peter Bauer ,  Karsten Braeuer ,  Marco Flach ,  Andreas Langner ,  Richard Schmidt ,  Clemens Schmitt ,  Gerhard Schoetz ,  Matthias Stecher

IPC: H01S3/06 ,  C03B37/075 ,  C03B37/012

CPC classification number: H01S3/0602 ,  C03B23/207 ,  C03B37/01245 ,  C03B2201/12 ,  C03B2203/02 ,  C03B2203/18 ,  C03B2203/34 ,  H01S3/063 ,  H01S3/06708 ,  H01S3/06745 ,  H01S3/094003 ,  H01S3/094007 ,  H01S3/1603 ,  H01S3/176

Abstract: Cylindrical optical components of quartz glass are known, which have an inner zone made of an inner zone glass, which extends in the direction of the longitudinal axis and is surrounded by a jacket zone made of a jacket zone glass, the average pt wall thickness thereof varying at least over a part of its length in the direction of the longitudinal axis of the component. The aim of the invention is to provide a method that allows a simple and cost-effective production of such an optical component from quartz glass. A method is proposed according to the invention, comprising the following method steps: (a) providing a first parison made of an inner zone glass, which has a first contact surface on the end face, said contact surface having a conical external contour; (b) providing a second parison from the jacket zone glass; (c) embedding the contact surface with a conical external contour into the jacket zone glass and welding the contact surface to the jacket zone glass, thereby forming a composite parison which has a cone-shaped inner zone area of inner zone glass in a contact area, said inner zone area being surrounded by a jacket zone having the shape of an inner cone; and (d) elongation of the composite parison to form the optical component or a preproduct of the component.

Abstract translation: 石英玻璃的圆柱形光学部件是已知的，其具有由内部区域玻璃制成的内部区域，该内部区域在纵向轴线的方向上延伸并被由夹套区域玻璃制成的护套区域围绕，其平均壁厚度 在组件的纵向轴线的方向上至少改变其长度的一部分。 本发明的目的是提供一种允许从石英玻璃简单且成本有效地生产这种光学部件的方法。 根据本发明提出了一种方法，包括以下方法步骤：（a）提供由内区玻璃制成的第一型坯，其在端面具有第一接触表面，所述接触表面具有锥形外轮廓; （b）从夹克区玻璃提供第二型坯; （c）将具有锥形外部轮廓的接触表面嵌入夹套区玻璃中并将接触表面焊接到护套区域玻璃上，由此形成复合型坯，其在接触区域中具有内部区域玻璃的锥形内部区域 所述内区域被具有内锥形状的护套区围绕; 和（d）复合型坯的伸长以形成光学部件或部件的前产物。

公开(公告)号：US08021929B2

公开(公告)日：2011-09-20

申请号：US12975825

申请日：2010-12-22

Applicant: Peter Nelle ,  Matthias Stecher

Inventor： Peter Nelle ,  Matthias Stecher

IPC: H01L21/00

CPC classification number: H01L23/49513 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/05624 ,  H01L2224/2908 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00015

Abstract: An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the lead frame. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.

Abstract translation: 公开了一种配置成降低热应力的装置和方法。 一个实施例提供半导体芯片，引线框架和层结构。 该层结构至少包括扩散焊料层和缓冲层。 层结构布置在半导体芯片和引线框架之间。 缓冲层包括与扩散焊料层的材料相比柔软的材料，并且包括使得在温度范围内的温度波动期间半导体芯片中的热应力保持低于预定值的层厚度。

公开(公告)号：US07851913B2

公开(公告)日：2010-12-14

申请号：US11602024

申请日：2006-11-20

Applicant: Thomas Gutt ,  Dirk Siepe ,  Thomas Laska ,  Michael Melzl ,  Matthias Stecher ,  Roman Roth

Inventor： Thomas Gutt ,  Dirk Siepe ,  Thomas Laska ,  Michael Melzl ,  Matthias Stecher ,  Roman Roth

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4807 ,  H01L2224/48458 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48757 ,  H01L2224/48764 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48857 ,  H01L2224/48864 ,  H01L2224/838 ,  H01L2224/85205 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/20752 ,  H01L2924/2076 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/48824 ,  H01L2224/48657 ,  H01L2924/00015

Abstract: A semiconductor device exhibits a first metal layer, made of a first metal, with at least one contiguous subsection. At least one second metal layer, made of a second metal, is placed on the contiguous subsection of the first metal layer. The second metal is harder than the first metal. The second metal layer is structured to form at least two layer regions, which are disposed on the contiguous subsection of the first metal layer. The second metal exhibits a boron-containing or phosphorus-containing metal or a boron-containing or phosphorus-containing metal alloy.

Abstract translation: 半导体器件具有由第一金属制成的具有至少一个连续部分的第一金属层。 由第二金属制成的至少一个第二金属层被放置在第一金属层的相邻子部分上。 第二种金属比第一种金属更硬。 第二金属层被构造成形成至少两个层区，它们设置在第一金属层的相邻子部分上。 第二金属表现出含硼或含磷金属或含硼或含磷金属合金。

公开(公告)号：US20100264508A1

公开(公告)日：2010-10-21

申请号：US12425988

申请日：2009-04-17

Applicant: Matthias Stecher ,  Hans-Joachim Schulze ,  Thomas Neidhart

Inventor： Matthias Stecher ,  Hans-Joachim Schulze ,  Thomas Neidhart

IPC: H01L29/06 ,  H01L21/76

CPC classification number: H01L21/823878 ,  H01L21/26506 ,  H01L21/743 ,  H01L21/761 ,  H01L27/0251 ,  H01L27/0921 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and manufacturing method is disclosed. One embodiment provides a common substrate of a first conductivity type and at least two wells of a second conductivity type. A buried high Ohmic region and at least an insulating structure is provided insulating the first well from the second well. The insulating structure extends through the buried high Ohmic region and includes a conductive plug in Ohmic contact with the first semiconductor region. A method for forming an integrated semiconductor device is also provided.

Abstract translation: 公开了一种半导体器件和制造方法。 一个实施例提供了第一导电类型的公共衬底和第二导电类型的至少两个阱。 提供掩埋的高欧姆区域和至少绝缘结构，其将第一井与第二井隔离。 绝缘结构延伸穿过埋入的高欧姆区域，并且包括与第一半导体区域欧姆接触的导电插塞。 还提供了一种用于形成集成半导体器件的方法。

公开(公告)号：US20090206420A1

公开(公告)日：2009-08-20

申请号：US12032760

申请日：2008-02-18

Applicant: Matthias Stecher ,  Tobias Smorodin

Inventor： Matthias Stecher ,  Tobias Smorodin

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L29/7809 ,  H01L23/4824 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/41741 ,  H01L29/41758 ,  H01L29/7395 ,  H01L29/7398 ,  H01L29/7802 ,  H01L29/7816 ,  H01L2924/0002 ,  H03K17/0822 ,  H01L2924/00

Abstract: A semiconductor device and method is disclosed. One embodiment provides an active region in a semiconductor substrate, including a first terminal region and a second terminal region. wherein the active region is interrupted by an inactive region, wherein an electrical power dissipation in the inactive region is zero or smaller than an electrical power dissipation in the active region; and a metallization layer arranged with respect to the active region on a surface of the semiconductor device and at least partly overlapping the active area, wherein the metallization layer is divided into a first part, in electrical contact to the first terminal region, and a second part, in electrical contact to the second terminal region, wherein the first and the second part are separated by a gap; and wherein the gap and the inactive region are mutually arranged so that an electrical power dissipation below the gap is reduced compared to an electrical power dissipation below the first part and the second part of the metallization layer.

Abstract translation: 公开了半导体器件和方法。 一个实施例提供半导体衬底中的有源区，包括第一端区和第二端区。 其中所述有源区域被非活性区域中断，其中所述无源区域中的功率消耗为零或小于所述有源区域中的功率耗散; 以及金属化层，其相对于所述半导体器件的表面上的所述有源区域布置并且至少部分地与所述有源区域重叠，其中所述金属化层被分成与所述第一端子区域电接触的第一部分，以及第二部分 部分地与第二端子区域电接触，其中第一和第二部分被间隙隔开; 并且其中所述间隙和所述非活性区域相互布置，使得与所述金属化层的第一部分和所述第二部分下方的电功率耗散相比，所述间隙之下的电功率耗散减小。

公开(公告)号：US07528010B2

公开(公告)日：2009-05-05

申请号：US11778887

申请日：2007-07-17

Applicant: Ralf Otremba ,  Josef Hoeglauer ,  Matthias Stecher

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Matthias Stecher

IPC: H01L21/00

CPC classification number: H01L23/552 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/29 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/13 ,  H01L24/73 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor component of semiconductor chip size includes a semiconductor chip. The semiconductor chip has a metallic coating that completely covers the edge sides and the rear side and partly covers the top side, on which surface-mountable external contacts are arranged. One aspect includes power semiconductor components, wherein the metallic coating connects a rear side electrode to one of the surface-mountable external contacts on the top side of a power semiconductor chip.

Abstract translation: 半导体芯片尺寸的半导体部件包括半导体芯片。 半导体芯片具有完全覆盖边缘侧和后侧的金属涂层，并且部分地覆盖顶面，其上布置有表面可安装的外部触点。 一个方面包括功率半导体部件，其中金属涂层将后侧电极连接到功率半导体芯片的顶侧上的可表面安装的外部触头之一。

公开(公告)号：US20090108421A1

公开(公告)日：2009-04-30

申请号：US11925268

申请日：2007-10-26

Applicant: Peter Nelle ,  Matthias Stecher

Inventor： Peter Nelle ,  Matthias Stecher

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/49513 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/05624 ,  H01L2224/2908 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00015

Abstract: An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the lead frame. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.

Abstract translation: 公开了一种配置成降低热应力的装置和方法。 一个实施例提供半导体芯片，引线框架和层结构。 该层结构至少包括扩散焊料层和缓冲层。 层结构布置在半导体芯片和引线框架之间。 缓冲层包括与扩散焊料层的材料相比柔软的材料，并且包括使得在温度范围内的温度波动期间半导体芯片中的热应力保持低于预定值的层厚度。