公开(公告)号：US09490123B2

公开(公告)日：2016-11-08

申请号：US14523334

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  David Paul Brunco

IPC: H01L21/20 ,  H01L21/70 ,  H01L21/762 ,  H01L21/36 ,  H01L21/302 ,  H01L21/461 ,  H01L21/02

CPC classification number: H01L21/02664 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02694

Abstract: One illustrative method disclosed herein includes, among other things, sequentially forming a first material layer, a first capping layer, a second material layer and a second capping layer above a substrate, wherein the first and second material layers are made of semiconductor material having a lattice constant that is different than the substrate, the first material layer is strained as deposited, and a thickness of the first material layer exceeds its critical thickness required to be stable and strained, performing an anneal process after which the strain in the first material layer is substantially relaxed through the formation of crystallographic defects that are substantially confined to the semiconducting substrate, the first material layer, the first capping layer and the second material layer, and forming additional epitaxial semiconductor material on an upper surface of the resulting structure.

Abstract translation: 本文公开的一种说明性方法包括在衬底上顺序地形成第一材料层，第一覆盖层，第二材料层和第二覆盖层，其中第一和第二材料层由半导体材料制成，其具有 晶格常数不同于衬底，第一材料层被应变成沉积，并且第一材料层的厚度超过其要求稳定和应变的临界厚度，进行退火工艺，之后第一材料层中的应变 通过形成基本上限制于半导体衬底，第一材料层，第一覆盖层和第二材料层的晶体缺陷，以及在所得结构的上表面上形成附加的外延半导体材料而基本上松弛。

公开(公告)号：US20160314968A1

公开(公告)日：2016-10-27

申请号：US15134693

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haeryong KIM ,  Hyeonjin Shin ,  Seongjun Park

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  C23C16/56 ,  C09D1/00

CPC classification number: H01L21/02568 ,  C09D1/00 ,  C23C16/305 ,  C23C16/56 ,  H01L21/0262 ,  H01L21/02664 ,  H01L29/42356 ,  H01L29/78681

Abstract: Provided are a composition for forming a layered transition metal chalcogenide compound layer and a method of forming a layered transition metal chalcogenide compound layer by using the composition. The composition includes at least one of a transition metal precursor represented by Formula 1 and a chalcogenide precursor represented by Formula 2. Ma(R1)6-b-c(H)b(R2)c  [Formula 1] wherein, in Formula 1, M, R1, R2, a, b, and c are the same as defined in the detailed description, and M′kX2  [Formula 2] wherein, in Formula 2, M′ and X are the same as defined in the detailed description.

公开(公告)号：US09472575B2

公开(公告)日：2016-10-18

申请号：US14615621

申请日：2015-02-06

Applicant: International Business Machines Corporation

Inventor： Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/02 ,  H01L21/308 ,  H01L21/324 ,  H01L21/306 ,  H01L21/762 ,  H01L21/225 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/845 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/02636 ,  H01L21/02664 ,  H01L21/2251 ,  H01L21/2254 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/308 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/7624 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: In an aspect of the present invention, a field-effect transistor (FET) structure is formed. The FET structure comprises a plurality of fins formed on a semiconductor substrate, wherein the plurality of fins includes a set of fins that include a base portion that is comprised of relaxed silicon-germanium (SiGe) and an upper portion that is comprised of semiconductor material. In one aspect, a first set of one or more fins that include an upper portion comprised of a first semiconductor material. In another aspect, a second set of one or more fins that include an upper portion comprised of a second semiconductor material.

Abstract translation: 在本发明的一个方面，形成场效应晶体管（FET）结构。 FET结构包括形成在半导体衬底上的多个翅片，其中多个翅片包括一组翅片，其包括由松弛的硅 - 锗（SiGe）构成的基部和由半导体材料构成的上部 。 一方面，包括由第一半导体材料构成的上部的一个或多个鳍片的第一组。 在另一方面，一种包括由第二半导体材料构成的上部的一个或多个翅片的第二组。

公开(公告)号：US09472401B2

公开(公告)日：2016-10-18

申请号：US14938657

申请日：2015-11-11

Applicant: IMEC VZW

Inventor： Daniele Chiappe

IPC: H01L21/02 ,  H01L21/324 ,  H01L29/24 ,  C01G39/02 ,  C01G39/06

CPC classification number: H01L21/02568 ,  C01G39/02 ,  C01G39/06 ,  C01P2002/82 ,  C01P2002/85 ,  C01P2004/04 ,  H01L21/02381 ,  H01L21/02614 ,  H01L21/02628 ,  H01L21/02664 ,  H01L21/324 ,  H01L29/24

Abstract: A method is provided for forming an unsupported MoS2 layer in an aqueous medium, the method comprising the steps of: providing an assembly of a Mo oxide layer on a Si substrate; annealing said assembly in presence of H2S at a temperature sufficient for forming a MoS2 layer; and contacting the annealed assembly with an aqueous medium. This unsupported MoS2 layer can then be transferred by dip-coating to another substrate such as a dielectric substrate.

Abstract translation: 提供了一种用于在水性介质中形成无支撑的MoS 2层的方法，所述方法包括以下步骤：在Si衬底上提供Mo氧化物层的组件; 在足以形成MoS 2层的温度下，在H 2 S存在下退火所述组件; 并使退火的组件与水性介质接触。 然后可以通过浸涂将另一衬底（例如电介质衬底）来转移该未支撑的MoS 2层。

公开(公告)号：US09455140B2

公开(公告)日：2016-09-27

申请号：US14525351

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L29/78 ,  H01L21/18

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02579 ,  H01L21/02664 ,  H01L21/18 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: One illustrative method disclosed herein includes, among other things, performing first and second in situ doping, epitaxial deposition processes to form first and second layers of in situ doped epi semiconductor material, respectively, above a semiconductor substrate, wherein one of the first and second layers has a high level of germanium and a low level of P-type dopant material and the other of the first and second layers has a low level of germanium and a high level of P-type dopant material, and performing a mixing thermal anneal process on the first and second layers so as to form the final silicon germanium material having a high level of germanium and a high level of P-type dopant material.

Abstract translation: 本文中公开的一种说明性方法包括进行第一和第二原位掺杂，外延沉积工艺以分别在半导体衬底之上形成第一和第二层原位掺杂的外延半导体材料，其中第一和第二 层具有高水平的锗和低水平的P型掺杂剂材料，并且第一和第二层中的另一层具有低水平的锗和高水平的P型掺杂剂材料，并且进行混合热退火工艺 在第一和第二层上形成具有高水平的锗和高水平的P型掺杂剂材料的最终硅锗材料。

公开(公告)号：US09450142B2

公开(公告)日：2016-09-20

申请号：US14926610

申请日：2015-10-29

Applicant: Tsinghua University ,  HON HAI PRECISION INDUSTRY CO., LTD.

Inventor： Yang Wei ,  Shou-Shan Fan

IPC: H01L21/20 ,  H01L33/00

CPC classification number: H01L33/0079 ,  H01L21/0237 ,  H01L21/02444 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02642 ,  H01L21/02647 ,  H01L21/02664 ,  H01L33/007

Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate having an epitaxial growth surface is provided. A carbon nanotube layer is placed on the epitaxial growth surface. An epitaxial layer is epitaxially grown on the buffer layer. The substrate and the carbon nanotube layer are removed to expose the epitaxial layer.

Abstract translation: 提供了制造外延结构的方法。 该方法包括以下步骤。 提供了具有外延生长面的基板。 将碳纳米管层置于外延生长表面上。 在缓冲层上外延生长外延层。 去除衬底和碳纳米管层以暴露外延层。

公开(公告)号：US09449820B2

公开(公告)日：2016-09-20

申请号：US14578833

申请日：2014-12-22

Applicant: International Business Machines Corporation

Inventor： Guy M. Cohen ,  Michael A. Guillorn ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/161 ,  H01L29/775 ,  H01L29/10 ,  H01L21/20 ,  H01L29/66

CPC classification number: H01L21/02603 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/2018 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1029 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/775

Abstract: Techniques for reducing nanowire dimension and pitch are provided. In one aspect, a pitch multiplication method for nanowires includes the steps of: providing an SOI wafer having an SOI layer separated from a substrate by a BOX, wherein the SOI layer includes Si; patterning at least one nanowire in the SOI layer, wherein the at least one nanowire as-patterned has a square cross-sectional shape with flat sides; growing epitaxial SiGe on the outside of the at least one nanowire using an epitaxial process selective for growth of the epitaxial SiGe on the flat sides of the at least one nanowire; removing the at least one nanowire selective to the epitaxial SiGe, wherein the epitaxial SiGe that remains includes multiple epitaxial SiGe wires having been formed in place of the at least one nanowire that has been removed.

Abstract translation: 提供了降低纳米线尺寸和间距的技术。 一方面，用于纳米线的间距倍增方法包括以下步骤：提供具有通过BOX从衬底分离的SOI层的SOI晶片，其中所述SOI层包括Si; 在SOI层中构图至少一个纳米线，其中所述至少一个图案化的纳米线具有平坦侧面的正方形横截面形状; 在所述至少一个纳米线的外侧使用选择性地用于在所述至少一个纳米线的平坦侧上生长所述外延SiGe的外延工艺来生长外延SiGe; 去除对外延SiGe选择性的至少一个纳米线，其中保留的外延SiGe包括已经形成的多个外延SiGe线来代替已被去除的至少一个纳米线。

公开(公告)号：US09449817B2

公开(公告)日：2016-09-20

申请号：US14586048

申请日：2014-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-jo Tak ,  Jae-won Lee ,  Young-soo Park ,  Jun-youn Kim

IPC: H01L21/20 ,  H01L21/02 ,  H01L33/00 ,  H01L33/12 ,  H01L33/32

CPC classification number: H01L21/0254 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/0259 ,  H01L21/02642 ,  H01L21/02664 ,  H01L33/007 ,  H01L33/12 ,  H01L33/32

Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.

公开(公告)号：US09444009B2

公开(公告)日：2016-09-13

申请号：US14028379

申请日：2013-09-16

Applicant: TOYODA GOSEI CO., LTD.

Inventor： Masao Kamiya ,  Koichi Goshonoo ,  Shingo Totani ,  Takashi Kawai ,  Takahiro Mori ,  Koji Hirata

IPC: H01L21/02 ,  H01L29/20 ,  H01L33/32 ,  H01L33/00 ,  H01L33/20

CPC classification number: H01L33/32 ,  H01L21/0237 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02664 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/20 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A group-III nitride compound semiconductor light emitting element includes a substrate that has a main face on which an concave and convex portion is formed, a group-III nitride compound semiconductor layer that is formed on the main face of the substrate, and a clearance that is formed between the substrate and the group-III nitride compound semiconductor layer at a first region of the semiconductor light emitting element. In the first region, a portion of the group-III nitride compound semiconductor layer and a portion of the clearance are disposed in a concave of the concave and convex portion on a section through two adjacent top portions of the concave and convex portion and a bottom portion located between the adjacent top portions.

Abstract translation: III族氮化物化合物半导体发光元件包括具有形成有凹部和凸部的主面的基板，形成在基板的主面上的III族氮化物化合物半导体层和间隙 其形成在所述半导体发光元件的第一区域的所述基板和所述III族氮化物化合物半导体层之间。 在第一区域中，III族氮化物化合物半导体层的一部分和间隙的一部分通过凹凸部的两个相邻顶部设置在凹凸部的凹部中，底部 部分位于相邻顶部之间。

公开(公告)号：US09443728B2

公开(公告)日：2016-09-13

申请号：US14461191

申请日：2014-08-15

Applicant: Applied Materials, Inc.

Inventor： Swaminathan T. Srinivasan ,  Atif M. Noori ,  David K. Carlson

IPC: H01L21/02 ,  H01L21/67 ,  H01L21/324

CPC classification number: H01L21/02664 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/324 ,  H01L21/3245 ,  H01L21/67011 ,  H01L21/67098 ,  H01L21/67115 ,  H01L21/6719 ,  H01L21/67207 ,  H01L21/67248

Abstract: Implementations of the present disclosure generally relate to methods and apparatus for forming a film on a substrate. More particularly, implementations of the present disclosure relate to methods and apparatus for heteroepitaxial growth of crystalline films. In one implementation, a method of heteroepitaxial deposition of a strain relaxed buffer (SRB) layer on a substrate is provided. The method comprises epitaxially depositing a buffer layer over a dissimilar substrate, rapidly heating the buffer layer to relax the buffer layer, rapidly cooling the buffer layer and determining whether the buffer layer has achieved a desired thickness.

Abstract translation: 本公开的实施方式一般涉及在基板上形成膜的方法和装置。 更具体地，本公开的实施方案涉及用于晶体膜的异质外延生长的方法和装置。 在一个实施方案中，提供了在衬底上的应变松弛缓冲层（SRB）层的异质外延沉积的方法。 该方法包括在不同的衬底上外延沉积缓冲层，快速加热缓冲层以使缓冲层松弛，快速冷却缓冲层，并确定缓冲层是否达到所需的厚度。