公开(公告)号：US09570574B1

公开(公告)日：2017-02-14

申请号：US15180171

申请日：2016-06-13

申请人： International Business Machines Corporation

发明人： Praneet Adusumilli ,  Veeraraghavan S. Basker ,  Huiming Bu ,  Zuoguang Liu

IPC分类号： H01L21/768 ,  H01L29/45 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/535

CPC分类号： H01L29/45 ,  H01L21/31051 ,  H01L21/31138 ,  H01L21/3213 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66795

摘要： A method of fabricating a contact above a source or drain region of an integrated circuit includes depositing a first liner conformally in a bottom and along a sidewall of a trench formed above the source or drain region, depositing a second liner conformally over the first liner, and stripping the first liner and the second liner from a portion of the sidewall from an opening of the trench to a height above the bottom of the trench. The method also includes depositing a third liner conformally over the second liner on the bottom and to the height above the bottom of the trench and on the portion of the sidewall, and depositing a metal fill to fill the trench.

摘要翻译： 一种在集成电路的源极或漏极区域上制造接触的方法包括：在底部和沿着形成在源极或漏极区域上方的沟槽的侧壁上共形沉积第一衬垫，在第一衬里上共形沉积第二衬垫， 以及从所述沟槽的开口的所述侧壁的一部分剥离所述第一衬垫和所述第二衬垫到所述沟槽的底部之上的高度。 该方法还包括将第三衬套在底部上平行地沉积在第二衬垫上方并且在沟槽的底部上方和在侧壁的部分上方的高度沉积，并且沉积金属填充物以填充沟槽。

公开(公告)号：US09496225B1

公开(公告)日：2016-11-15

申请号：US15018387

申请日：2016-02-08

申请人： International Business Machines Corporation

发明人： Praneet Adusumilli ,  Veeraraghavan S. Basker ,  Huiming Bu ,  Zuoguang Liu

IPC分类号： H01L23/48 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L29/45 ,  H01L21/31051 ,  H01L21/31138 ,  H01L21/3213 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66795

摘要： A method of fabricating a contact above a source or drain region of an integrated circuit includes depositing a first liner conformally in a bottom and along a sidewall of a trench formed above the source or drain region, depositing a second liner conformally over the first liner, and stripping the first liner and the second liner from a portion of the sidewall from an opening of the trench to a height above the bottom of the trench. The method also includes depositing a third liner conformally over the second liner on the bottom and to the height above the bottom of the trench and on the portion of the sidewall, and depositing a metal fill to fill the trench.

摘要翻译： 一种在集成电路的源极或漏极区域上制造接触的方法包括：在底部和沿着形成在源极或漏极区域上方的沟槽的侧壁上共形沉积第一衬垫，在第一衬里上共形沉积第二衬垫， 以及从所述沟槽的开口的所述侧壁的一部分剥离所述第一衬垫和所述第二衬垫到所述沟槽的底部之上的高度。 该方法还包括将第三衬套在底部上平行地沉积在第二衬垫上方并且在沟槽的底部上方和在侧壁的部分上方的高度沉积，并且沉积金属填充物以填充沟槽。

公开(公告)号：US09478490B2

公开(公告)日：2016-10-25

申请号：US14483110

申请日：2014-09-10

申请人： QUALCOMM Incorporated

发明人： John Jianhong Zhu ,  Stanley Seungchul Song ,  Kern Rim ,  Zhongze Wang ,  Jeffrey Junhao Xu

IPC分类号： H01L21/02 ,  H01L27/108 ,  H01L21/00 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/08

CPC分类号： H01L23/5223 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/823475 ,  H01L27/0805 ,  H01L28/60 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device capacitor structure within middle of line (MOL) layers includes a first MOL interconnect layer. The first MOL interconnect layer may include active contacts between a set of dummy gate contacts on an active surface of a semiconductor substrate. The device capacitor structure also includes a second MOL interconnect layer. The second MOL interconnect layer may include a set of stacked contacts directly on exposed ones of the active contacts. The second MOL interconnect layer may also include a set of fly-over contacts on portions of an etch-stop layer on some of the active contacts. The fly-over contacts and the stacked contacts may provide terminals of a set of device capacitors.

摘要翻译： 线路（MOL）层中间的器件电容器结构包括第一MOL互连层。 第一MOL互连层可以包括半导体衬底的有源表面上的一组虚拟栅极触点之间的有源触点。 器件电容器结构还包括第二MOL互连层。 第二MOL互连层可以直接在活动触点的暴露的一个上包括一组堆叠的触点。 第二MOL互连层还可以包括在一些有源触点上的蚀刻停止层的部分上的一组飞越触点。 飞越触点和堆叠的触点可以提供一组器件电容器的端子。

公开(公告)号：US09425044B2

公开(公告)日：2016-08-23

申请号：US14461565

申请日：2014-08-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Hsing Chang ,  Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC分类号： H01L29/788 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115

CPC分类号： H01L21/02601 ,  H01L21/02532 ,  H01L21/28273 ,  H01L21/3213 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7881

摘要： Some embodiments relate to a memory device comprising a charge-trapping layer disposed between a control gate and a select gate. A capping structure is disposed over an upper surface of the control gate, and a composite spacer is disposed on a source-facing sidewall surface of the control gate. The capping structure and the composite spacer prevent damage to the control gate during one more etch processes used for contact formation to the memory device. To further limit or prevent the select gate sidewall etching, some embodiments provide for an additional liner oxide layer disposed along the drain-facing sidewall surface of the select gate. The liner oxide layer is configured as an etch stop layer to prevent etching of the select gate during the one or more etch processes. As a result, the one or more etch processes leave the control gate and select gate substantially intact.

摘要翻译： 一些实施例涉及包括设置在控制栅极和选择栅极之间的电荷捕获层的存储器件。 封盖结构设置在控制栅极的上表面上，并且复合间隔物设置在控制栅极的面向源的侧壁表面上。 封盖结构和复合间隔物在用于与存储器件的接触形成的一个以上蚀刻工艺期间防止对控制栅极的损坏。 为了进一步限制或防止选择栅极侧壁蚀刻，一些实施例提供沿着选择栅极的面向排水的侧壁表面设置的附加衬垫氧化物层。 衬里氧化物层被配置为蚀刻停止层，以防止在一个或多个蚀刻工艺期间蚀刻选择栅极。 结果，一个或多个蚀刻工艺离开控制栅极并基本上完整地选择栅极。

公开(公告)号：US20160240539A1

公开(公告)日：2016-08-18

申请号：US14620480

申请日：2015-02-12

申请人： QUALCOMM Incorporated

发明人： Niladri Narayan Mojumder ,  Ritu Chaba ,  Ping Liu ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC分类号： H01L27/11 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L27/1104 ,  G11C8/14 ,  G11C8/16 ,  G11C11/418 ,  G11C11/419 ,  H01L21/3213 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11

摘要： An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.

摘要翻译： 一种装置包括耦合到位单元的第一金属层。 该装置还包括第三金属层，其包括耦合到位单元的写入字线。 该装置还包括在第一金属层和第三金属层之间的第二金属层。 第二金属层包括耦合到位单元的两个读字线。

公开(公告)号：US09380709B2

公开(公告)日：2016-06-28

申请号：US13924681

申请日：2013-06-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chin-Hsiung Hsu ,  Huang-Yu Chen ,  Tsong-Hua Ou ,  Wen-Hao Chen

IPC分类号： H05K3/10 ,  H05K3/06 ,  H05K3/00

CPC分类号： G03F7/2022 ,  G03F1/70 ,  G06F17/5068 ,  H01L21/3213 ,  H05K3/0005 ,  H05K3/0082 ,  H05K3/06 ,  H05K3/068 ,  H05K2201/09781 ,  H05K2203/0557 ,  H05K2203/1476 ,  Y10T29/49156

摘要： A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.

摘要翻译： 一种方法包括用第一金属图案在衬底上图案化层; 在相对于所述基板的第一位置使用切割掩模，以执行用于从所述第一图案内的第一区域去除材料的第一切割图案; 并且使用相同的切割掩模在相对于衬底上的相同层的第二位置执行第二切割图案，用于从衬底上的相同层的第二金属图案中的第二区域去除材料。

公开(公告)号：US20160141208A1

公开(公告)日：2016-05-19

申请号：US14541239

申请日：2014-11-14

申请人： INFINEON TECHNOLOGIES AG

发明人： Hirschler Joachim ,  Roesner Michael ,  Heinrici Juch Markus ,  Stranzl Gudrun ,  Mischitz Martin ,  Zgaga Martin

IPC分类号： H01L21/78 ,  H01L21/324 ,  H01L23/29 ,  H01L21/3213

CPC分类号： H01L21/78 ,  H01L21/288 ,  H01L21/3213 ,  H01L21/6835 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/94 ,  H01L24/95 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2224/03002 ,  H01L2224/03005 ,  H01L2224/03009 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/03505 ,  H01L2224/03848 ,  H01L2224/039 ,  H01L2224/05794 ,  H01L2224/05847 ,  H01L2224/06181 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2221/68381

摘要： According to various embodiments, a method for processing a semiconductor substrate may include: covering a plurality of die regions of the semiconductor substrate with a metal; forming a plurality of dies from the semiconductor substrate, wherein each die of the plurality of dies is covered with the metal; and, subsequently, annealing the metal covering at least one die of the plurality of dies.

摘要翻译： 根据各种实施例，用于处理半导体衬底的方法可以包括：用金属覆盖半导体衬底的多个管芯区域; 从所述半导体衬底形成多个管芯，其中所述多个管芯中的每个管芯被所述金属覆盖; 并且随后对所述多个管芯中的至少一个管芯进行金属覆盖退火。

公开(公告)号：US20160141179A1

公开(公告)日：2016-05-19

申请号：US14588223

申请日：2014-12-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Nan Wu ,  Shiu-Ko JangJian ,  Chun Che Lin ,  W.C. HsuKu

IPC分类号： H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/285 ,  H01L21/3213

CPC分类号： H01L29/7851 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/3212 ,  H01L21/3213 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53266 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

摘要： An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.

摘要翻译： 提供了用于半导体器件的改进的导电特征和用于形成该特征的技术。 在示例性实施例中，半导体器件包括其上形成有栅极结构的衬底。 栅极结构包括设置在基板上的栅极电介质层，设置在栅极结构的侧表面上的生长控制材料和设置在生长控制材料上的栅电极填充材料。 栅极电极填充材料也设置在栅极结构的没有生长控制材料的底表面上。 在一些这样的实施例中，栅电极填充材料接触组成不同的第一表面和第二表面。

公开(公告)号：US20160104837A1

公开(公告)日：2016-04-14

申请号：US14972152

申请日：2015-12-17

申请人： Micron Technology, Inc.

发明人： Marcello Ravasio ,  Samuele Sciarrillo ,  Andrea Gotti

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/124 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/1052 ,  H01L27/222 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

摘要： Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.

公开(公告)号：US20160093560A1

公开(公告)日：2016-03-31

申请号：US14500982

申请日：2014-09-29

申请人： Alpha and Omega Semiconductor (Cayman) Ltd.

发明人： Yan Huo ,  Hamza Yilmaz ,  Jun Lu ,  Ming-Chen Lu ,  Zhi Qiang Niu ,  Yan Xun Xue ,  Demei Gong

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L21/3105 ,  H01L21/78 ,  H01L21/48 ,  H01L21/3213 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L23/49541 ,  H01L21/31053 ,  H01L21/3213 ,  H01L21/4842 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/11 ,  H01L24/14 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/1184 ,  H01L2224/32245 ,  H01L2224/73153 ,  H01L2924/01013 ,  H01L2924/05432 ,  H01L2924/13091 ,  H01L2924/00

摘要： An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame unit and then a plurality of metal bumps are deposited, where one metal bump is formed on each contact hole on the upper section and on each of the electrodes on the top surface of the semiconductor chip.

摘要翻译： 公开了一种具有高散热性能的超薄功率半导体封装及其制备方法。 该包装包括具有交错结构的引线框单元，包括上部和下部。 引线框架单元的表面上附着一薄层，该上表面具有在上部上的多个接触孔和下部的至少一个开口。 半导体芯片安装在引线框架单元的下部的开口上，然后沉积多个金属凸块，其中在上部的每个接触孔和顶部的每个电极上形成一个金属凸块 半导体芯片的表面。