公开(公告)号：US08569086B2

公开(公告)日：2013-10-29

申请号：US13216825

申请日：2011-08-24

申请人： Jing-Cheng Lin ,  Chih-Wei Wu ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Chih-Wei Wu ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/00

CPC分类号： H01L23/49816 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/73204 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method and apparatus for separating a substrate into individual dies and the resulting structure is provided. A modification layer, such as an amorphous layer, is formed within the substrate. A laser focused within the substrate may be used to create the modification layer. The modification layer creates a relatively weaker region that is more prone to cracking than the surrounding substrate material. As a result, the substrate may be pulled apart into separate sections, causing cracks the substrate along the modification layers. Dice or other components may be attached to the substrate before or after separation.

摘要翻译： 提供了一种用于将基底分离成单个模具的方法和装置，并且提供了所得到的结构。 在衬底内形成诸如非晶层的改性层。 可以使用聚焦在衬底内的激光来产生修饰层。 改性层产生比周围的基材更容易破裂的相对较弱的区域。 结果，衬底可以被拉开到分开的部分中，从而沿着修饰层裂开衬底。 在分离之前或之后，骰子或其它组分可附着于基底。

公开(公告)号：US08557684B2

公开(公告)日：2013-10-15

申请号：US13215959

申请日：2011-08-23

申请人： Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/301

CPC分类号： H01L21/78 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/85 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method includes performing a laser grooving to remove a dielectric material in a wafer to form a trench, wherein the trench extends from a top surface of the wafer to stop at an intermediate level between the top surface and a bottom surface of the wafer. The trench is in a scribe line between two neighboring chips in the wafer. A polymer is filled into the trench and then cured. After the step of curing the polymer, a die saw is performed to separate the two neighboring chips, wherein a kerf line of the die saw cuts through a portion of the polymer filled in the trench.

摘要翻译： 一种方法包括执行激光切槽以去除晶片中的电介质材料以形成沟槽，其中沟槽从晶片的顶表面延伸以在晶片的顶表面和底表面之间的中间水平处停止。 沟槽在晶片中的两个相邻芯片之间的划线中。 将聚合物填充到沟槽中，然后固化。 在固化聚合物的步骤之后，执行模锯以分离两个相邻的芯片，其中模具的切口线切割填充在沟槽中的聚合物的一部分。

公开(公告)号：US08525343B2

公开(公告)日：2013-09-03

申请号：US12892409

申请日：2010-09-28

申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Ebin Liao ,  Tsang-Jiuh Wu

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Ebin Liao ,  Tsang-Jiuh Wu

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76831 ,  H01L21/486 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00

摘要： A device with through-silicon via (TSV) and a method of forming the same includes the formation of an opening in a silicon substrate, the formation of a first insulation layer on the sidewalls and bottom of the opening, the formation of a second insulation layer on the sidewalls and bottom of the opening. A first interface between the first insulation layer and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm. A second interface between the second insulation layer and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm.

摘要翻译： 具有通硅通孔（TSV）的器件及其形成方法包括在硅衬底中形成开口，在开口的侧壁和底部形成第一绝缘层，形成第二绝缘体 层在开口的侧壁和底部。 第一绝缘层和硅衬底之间的第一界面具有峰 - 谷高度小于5nm的界面粗糙度。 第二绝缘层与导电层之间的第二界面具有峰 - 谷高度小于5nm的界面粗糙度。

公开(公告)号：US08519414B2

公开(公告)日：2013-08-27

申请号：US13237181

申请日：2011-09-20

申请人： Chia-Lin Yu ,  Ding-Yuan Chen ,  Chen-Hua Yu ,  Wen-Chih Chiou

发明人： Chia-Lin Yu ,  Ding-Yuan Chen ,  Chen-Hua Yu ,  Wen-Chih Chiou

IPC分类号： H01L27/15

CPC分类号： H01L33/04 ,  H01L33/12 ,  H01L33/32

摘要： A semiconductor structure includes a substrate and a conductive carrier-tunneling layer over and contacting the substrate. The conductive carrier-tunneling layer includes first group-III nitride (III-nitride) layers having a first bandgap, wherein the first III-nitride layers have a thickness less than about 5 nm; and second III-nitride layers having a second bandgap lower than the first bandgap, wherein the first III-nitride layers and the second III-nitride layers are stacked in an alternating pattern. The semiconductor structure is free from a III-nitride layer between the substrate and the conductive carrier-tunneling layer. The semiconductor structure further includes an active layer over the conductive carrier-tunneling layer.

摘要翻译： 半导体结构包括衬底和与衬底接触的导电载体隧穿层。 导电载体隧穿层包括具有第一带隙的第一III族氮化物（III族氮化物）层，其中第一III族氮化物层具有小于约5nm的厚度; 和具有比第一带隙低的第二带隙的第二III族氮化物层，其中第一III族氮化物层和第二III族氮化物层以交替图案堆叠。 半导体结构在衬底和导电载体 - 隧穿层之间不含III族氮化物层。 半导体结构还包括在导电载体 - 隧穿层上的有源层。

公开(公告)号：US08507940B2

公开(公告)日：2013-08-13

申请号：US12879584

申请日：2010-09-10

申请人： Chen-Hua Yu ,  Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Pin Hung ,  Chien Ling Hwang

发明人： Chen-Hua Yu ,  Hung-Pin Chang ,  Yung-Chi Lin ,  Chia-Lin Yu ,  Jui-Pin Hung ,  Chien Ling Hwang

IPC分类号： H01L33/00

CPC分类号： H01L21/76898 ,  H01L21/3065 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L33/005 ,  H01L33/0054 ,  H01L33/486 ,  H01L33/62 ,  H01L33/641 ,  H01L33/644 ,  H01L33/647 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2933/0066 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The package substrates with through silicon plugs (or vias) described above provide lateral and vertical heat dissipation pathways for semiconductor chips that require thermal management. Designs of through silicon plugs (TSPs) with high duty ratios can most effectively provide heat dissipation. TSP designs with patterns of double-sided combs can provide high duty ratios, such as equal to or greater than 50%. Package substrates with high duty ratios are useful for semiconductor chips that generate large amount of heat. An example of such semiconductor chip is a light-emitting diode (LED) chip.

摘要翻译： 具有上述通孔硅封装（或通孔）的封装衬底为需要热管理的半导体芯片提供侧向和垂直散热​​路径。 具有高占空比的通过硅插头（TSP）的设计可以最有效地提供散热。 具有双面梳状图案的TSP设计可以提供等于或大于50％的高占空比。 具有高占空比的封装衬底对于产生大量热量的半导体芯片是有用的。 这种半导体芯片的例子是发光二极管（LED）芯片。

公开(公告)号：US08486807B2

公开(公告)日：2013-07-16

申请号：US12972184

申请日：2010-12-17

申请人： Chen-Hua Yu ,  Chia-Lin Yu ,  Ding-Yuan Chen ,  Wen-Chih Chiou

发明人： Chen-Hua Yu ,  Chia-Lin Yu ,  Ding-Yuan Chen ,  Wen-Chih Chiou

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/02617 ,  H01L21/02664

摘要： A method of forming a semiconductor structure includes providing a substrate; forming a buffer/nucleation layer over the substrate; forming a group-III nitride (III-nitride) layer over the buffer/nucleation layer; and subjecting the III-nitride layer to a nitridation. The step of forming the III-nitride layer comprises metal organic chemical vapor deposition.

摘要翻译： 形成半导体结构的方法包括提供基板; 在衬底上形成缓冲/成核层; 在缓冲/成核层上形成III族氮化物（III族氮化物）层; 并对该III族氮化物层进行氮化。 形成III族氮化物层的步骤包括金属有机化学气相沉积。

公开(公告)号：US20130175700A1

公开(公告)日：2013-07-11

申请号：US13346398

申请日：2012-01-09

申请人： Ming-Fa Chen ,  Chen-Hua Yu ,  Sen-Bor Jan

发明人： Ming-Fa Chen ,  Chen-Hua Yu ,  Sen-Bor Jan

IPC分类号： H01L23/522 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/565 ,  H01L21/566 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/17 ,  H01L24/94 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

摘要： A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.

摘要翻译： 提供了一种用于连接半导体管芯的系统和方法。 一个实施例包括将具有第一宽度的第一半导体管芯连接到具有较大第二宽度的第二半导体管芯，并且仍然连接到半导体晶片。 第一半导体管芯在其连接之后被封装，并且密封剂和第一半导体管芯被减薄以在第一半导体管芯内经由衬底暴露。 第二半导体管芯从半导体晶片分离，然后将组合的第一半导体管芯和第二半导体管芯连接到另一个衬底。

公开(公告)号：US20130140713A1

公开(公告)日：2013-06-06

申请号：US13308742

申请日：2011-12-01

申请人： Chen-Hua Yu ,  Chien-Chia Chiu ,  Cheng-Chieh Hsieh

发明人： Chen-Hua Yu ,  Chien-Chia Chiu ,  Cheng-Chieh Hsieh

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L24/75 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/73267 ,  H01L2224/757 ,  H01L2224/75743 ,  H01L2224/7598 ,  H01L2224/81002 ,  H01L2224/81132 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/95146 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

摘要： The present disclosure relates to a method for fast and precise alignment and mounting of a top die onto an interposer wafer. The method is performed by applying a hydrophobic self assembled monolayer to a carrier wafer in a pattern defining a top die placement region correlating to an arrangement of a top die on an interposer wafer. A liquid is provided into the top die placement region and a top die is placed into contact with the liquid. The surface tension of the liquid automatically aligns the top die by generating a force causing the top die to overlap with the top die placement region. The liquid is then eliminated and the top die is affixed to the carrier wafer. The carrier wafer is bonded to the interposer wafer, bringing the top die into contact with an interposer.

摘要翻译： 本公开涉及一种用于将顶模快速且精确地对准和安装到插入器晶片上的方法。 该方法通过将疏水性自组装单层以限定与插入物晶片上的顶模的布置相关的顶模放置区的图案施加于载体晶片来进行。 将液体提供到顶部模具放置区域中，并且顶部模具被放置成与液体接触。 液体的表面张力通过产生导致顶模与顶模放置区重叠的力自动对准顶模。 然后消除液体，并将顶模固定到载体晶片上。 载体晶片结合到插入器晶片，使顶模与插入件接触。

公开(公告)号：US20130122659A1

公开(公告)日：2013-05-16

申请号：US13296922

申请日：2011-11-15

申请人： Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/56

CPC分类号： H01L24/97 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method comprises attaching a first side of an interposer on a carrier wafer. The first side of the interposer comprises a plurality of bumps. The carrier wafer comprises a plurality of cavities formed in the carrier wafer. Each bump on the first side of the interposer can fit into its corresponding cavity on the carrier wafer. Subsequently, the method comprises attaching a semiconductor die on the second side of the interposer to form a wafer stack, detaching the wafer stack from the carrier wafer and attaching the wafer stack to a substrate.

摘要翻译： 一种方法包括将插入件的第一侧附着在载体晶片上。 插入器的第一侧包括多个凸块。 载体晶片包括形成在载体晶片中的多个空腔。 插入器的第一侧上的每个凸块可以装配到载体晶片上的相应空腔中。 随后，该方法包括在插入器的第二侧上附加半导体管芯以形成晶片堆叠，将晶片堆叠与载体晶片分离并将晶片堆叠连接到基板。

公开(公告)号：US08440564B2

公开(公告)日：2013-05-14

申请号：US13551500

申请日：2012-07-17

申请人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

发明人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L21/44

CPC分类号： H01L23/53238 ,  H01L21/322 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.