公开(公告)号：US07067398B2

公开(公告)日：2006-06-27

申请号：US11103464

申请日：2005-04-12

申请人： Hideo Aoki ,  Naoko Yamaguchi ,  Chiaki Takubo ,  Toshiaki Yamauchi ,  Koji Imamiya ,  Hiroshi Hashizume

发明人： Hideo Aoki ,  Naoko Yamaguchi ,  Chiaki Takubo ,  Toshiaki Yamauchi ,  Koji Imamiya ,  Hiroshi Hashizume

IPC分类号： H01L21/283

CPC分类号： H05K3/246 ,  G03G15/224 ,  G03G15/225 ,  G03G15/6585 ,  G03G15/6591 ,  H01L21/4846 ,  H01L2924/0002 ,  H05K1/095 ,  H05K3/1266 ,  H05K3/242 ,  H05K2201/0347 ,  H05K2203/0517 ,  Y10S438/951 ,  H01L2924/00

摘要： According to an embodiment of the present invention, a method of producing an electronic circuit comprises printing first metal-containing resin particles which consist of at least a thermosetting resin and fine metal particles and second metal-containing resin particles which consist of at least a thermoplastic resin and fine metal particles by electrophotography to form a first base pattern which consists of the first metal-containing resin particles and a second base pattern which consists of the second metal-containing resin particles on a substrate; forming a first metal conductor layer on the first and second base patterns; forming a second metal conductor layer on the first metal conductor layer by electrolytic plating by supplying electric current to the first metal conductor layer; and removing the second base pattern and the first and second metal conductor layers which are formed on the second base pattern.

摘要翻译： 根据本发明的一个实施方案，电子电路的制造方法包括：将至少由热固性树脂和细金属颗粒构成的第一含金属树脂颗粒和由至少由热塑性塑料构成的第二含金属树脂颗粒 树脂和细金属颗粒，以形成由第一含金属的树脂颗粒和由基材上的第二含金属的树脂颗粒组成的第二基底图案的第一基底图案; 在所述第一和第二基底图案上形成第一金属导体层; 通过向第一金属导体层提供电流通过电解电镀在第一金属导体层上形成第二金属导体层; 以及去除形成在第二基底图案上的第二基底图案和第一和第二金属导体层。

公开(公告)号：US20050227158A1

公开(公告)日：2005-10-13

申请号：US11081029

申请日：2005-03-16

申请人： Toshiaki Yamauchi ,  Koji Imamiya ,  Hiroshi Hashizume ,  Hideo Aoki ,  Naoko Yamaguchi ,  Chiaki Takubo

发明人： Toshiaki Yamauchi ,  Koji Imamiya ,  Hiroshi Hashizume ,  Hideo Aoki ,  Naoko Yamaguchi ,  Chiaki Takubo

IPC分类号： G03G9/08 ,  G03G9/09 ,  G03G9/097 ,  G03G15/20 ,  H05K1/09 ,  H05K3/10 ,  H05K3/24

CPC分类号： G03G9/0819 ,  G03G9/0926 ,  G03G9/09708 ,  G03G15/225 ,  G03G15/6585 ,  H05K1/095 ,  H05K3/1266 ,  H05K3/246 ,  H05K2201/0209 ,  H05K2201/0215 ,  H05K2201/0347 ,  H05K2203/0517

摘要： A conductive underlayer is formed in an electrophotographic manner using a toner comprising toner particles containing a binder resin containing a green thermosetting resin and conductive particles having an average particle diameter of 0.05 μm to 1 μm, wherein 50% by volume particle diameter of the toner is in a range 4 μm to 12 μm and the ratio of the toner with a size of 4 μm or smaller is 20% by number or less, or a toner including external additives containing hydrophobic-treated small size metal oxide particles having a BET specific surface area of 150 m2/g to 400 m2/g and large size metal oxide particles having a BET specific surface area of 10 m2/g to 70 m2/g and then a conductive layer is formed thereon by plating.

摘要翻译： 使用包含含有包含绿色热固性树脂的粘合剂树脂的调色剂颗粒和平均粒径为0.05μm至1μm的导电颗粒的调色剂形成导电底层，其中调色剂的50体积％粒径为 在4μm至12μm的范围内，并且4μm或更小的尺寸的调色剂的比例为20数量％或更少，或包含含有具有BET比表面积的疏水处理的小尺寸金属氧化物颗粒的外部添加剂的调色剂 150m 2 / g至400m 2 / g的面积和BET比表面积为10m 2 / g的大尺寸金属氧化物颗粒， g至70m 2 / g，然后通过电镀在其上形成导电层。

公开(公告)号：US20050199989A1

公开(公告)日：2005-09-15

申请号：US11075421

申请日：2005-03-09

申请人： Hideo Aoki ,  Yoshiaki Sugizaki ,  Naoko Yamaguchi ,  Chiaki Takubo

发明人： Hideo Aoki ,  Yoshiaki Sugizaki ,  Naoko Yamaguchi ,  Chiaki Takubo

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L25/00

CPC分类号： H01L23/49883 ,  H01L21/4867 ,  H01L21/563 ,  H01L22/14 ,  H01L22/20 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/98 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14135 ,  H01L2224/14156 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/81026 ,  H01L2224/81097 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/818 ,  H01L2224/83886 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/05599

摘要： According to one aspect of the present invention, a semiconductor device, comprising a wiring board provided with wires and electrodes; a semiconductor element which is mounted on the wiring board and has plural connection electrodes formed on its surface; and a metal layer of fine metal particles aggregated and bonded which is interposed between the electrodes on the wiring board and the connection electrodes of the semiconductor element to connect between the electrodes and the connection electrodes, is provided.

摘要翻译： 根据本发明的一个方面，提供了一种半导体器件，包括：布线板，其配有导线和电极; 半导体元件，其安装在所述布线板上，并且在其表面上形成有多个连接电极; 并且设置介于导线板上的电极和半导体元件的连接电极之间聚集和结合的金属微粒金属层，以连接电极和连接电极。

公开(公告)号：US06617678B2

公开(公告)日：2003-09-09

申请号：US10145722

申请日：2002-05-16

申请人： Takashi Yamazaki ,  Mitsuyoshi Endo ,  Chiaki Takubo ,  Katsuhiko Oyama ,  Takashi Imoto ,  Mikio Matsui

发明人： Takashi Yamazaki ,  Mitsuyoshi Endo ,  Chiaki Takubo ,  Katsuhiko Oyama ,  Takashi Imoto ,  Mikio Matsui

IPC分类号： H01L2302

CPC分类号： H01L25/0657 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： There is disclosed a semiconductor device which comprises a first chip-mounting substrate on which at least one semiconductor chip having a plurality of terminals is mounted, and a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, a second chip-mounting substrate which is laminated on the first chip-mounting substrate and on which at least one semiconductor chip is mounted, a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, and at least one of the semiconductor chips has a center offset from a center of a whole arrangement of the relay terminals.

公开(公告)号：US06271478B1

公开(公告)日：2001-08-07

申请号：US09195831

申请日：1998-11-19

申请人： Michio Horiuchi ,  Yukiharu Takeuchi ,  Chiaki Takubo

发明人： Michio Horiuchi ,  Yukiharu Takeuchi ,  Chiaki Takubo

IPC分类号： H05K114

CPC分类号： H05K1/112 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K2201/09227 ,  H05K2201/10734

摘要： A multi-layer circuit board having a decreased number of circuit boards for mounting an electronic part that has connection electrodes arranged in the form of an area array, featuring a high yield and improved reliability. In the multi-layer circuit board, circuit patterns formed on a first circuit board on the surface of the side where said electronic part is mounted, are connected to every land positioned on the outermost side of the lands arranged in the form of an area array, and are connected to the lands alternatingly selected from the lands of the second sequence and the third sequence of the inner side; circuit patterns formed on a second circuit board are connected to every via electrically connected to the lands of the second sequence to which the circuit pattern is not connected on the first circuit board, and to the vias electrically connected to all of the lands of the fourth sequence and the fifth sequence on the first circuit board; circuit patterns formed on a third circuit board are connected to every via electrically connected to the lands of the third sequence to which the circuit pattern is not connected on the first circuit board, and to the vias electrically connected to all of the lands of the sixth sequence and the seventh sequence on the first circuit board; and circuit patterns formed on a fourth circuit board are connected to every via electrically connected to the lands of the eighth sequence and the ninth sequence on the first circuit board.

摘要翻译： 一种多层电路板，其具有用于安装具有以区域阵列形式布置的连接电极的电子部件的电路板数量减少，具有高产量和改善的可靠性。 在多层电路板中，形成在安装有所述电子部件的一侧的表面上的第一电路板上的电路图案连接到位于以区域阵列形式布置的焊盘的最外侧的每个区域 并且连接到从第二序列的焊盘和内侧的第三序列交替地选择的焊盘; 形成在第二电路板上的电路图案连接到电连接到第一电路板上未连接电路图案的第二序列的焊盘的每个通孔，以及电连接到第四电路板的所有焊盘的通孔 序列和第一个电路板上的第五个序列; 形成在第三电路板上的电路图案连接到电连接到第一电路板上未连接电路图案的第三序列的焊盘的每个通孔，以及电连接到第六电路板的所有焊盘的通孔 序列和第七个序列在第一个电路板上; 并且形成在第四电路板上的电路图案连接到电连接到第一电路板上的第八序列和第九序列的焊盘的每个通孔。

公开(公告)号：US6111317A

公开(公告)日：2000-08-29

申请号：US784814

申请日：1997-01-16

申请人： Takashi Okada ,  Naohiko Hirano ,  Hiroshi Tazawa ,  Eiichi Hosomi ,  Chiaki Takubo ,  Kazuhide Doi ,  Yoichi Hiruta ,  Koji Shibasaki

发明人： Takashi Okada ,  Naohiko Hirano ,  Hiroshi Tazawa ,  Eiichi Hosomi ,  Chiaki Takubo ,  Kazuhide Doi ,  Yoichi Hiruta ,  Koji Shibasaki

IPC分类号： H01L23/485 ,  H01L23/528 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14

摘要： A first insulating film is formed on an integrated circuit chip on which an I/O pad is formed. A first opening portion is formed above the I/O pad. A conductive layer and a barrier metal layer which are electrically connected to the I/O pad through the first opening portion are stacked on the first insulating film. The conductive layer and the barrier metal layer are patterned by a single mask. A second insulating film is formed on the resultant structure. A second opening portion is formed in the second insulating film at a position different from that of the first opening portion. A solder bump or metal pad is formed on the barrier metal layer in the second opening portion. The position of the solder bump or metal pad is defined by the second opening portion.

摘要翻译： 在其上形成有I / O焊盘的集成电路芯片上形成第一绝缘膜。 第一开口部分形成在I / O焊盘上方。 通过第一开口部分电连接到I / O焊盘的导电层和阻挡金属层堆叠在第一绝缘膜上。 导电层和阻挡金属层通过单个掩模图案化。 在所得结构上形成第二绝缘膜。 在第二绝缘膜上形成与第一开口部不同的位置的第二开口部。 在第二开口部分的阻挡金属层上形成焊料凸块或金属焊盘。 焊料凸块或金属焊盘的位置由第二开口部分限定。

公开(公告)号：US6094057A

公开(公告)日：2000-07-25

申请号：US730816

申请日：1996-10-17

申请人： Yoichi Hiruta ,  Chiaki Takubo

发明人： Yoichi Hiruta ,  Chiaki Takubo

IPC分类号： G01R31/26 ,  G01R1/04 ,  H01L21/66 ,  G01R1/073 ,  G01R31/02

CPC分类号： G01R1/0483 ,  H01L2224/16225 ,  H01L2924/00014

摘要： A board body constituting a characteristic evaluation board has a holding section for holding a semiconductor chip therein. The semiconductor chip has a plurality of bumps. The respective bumps of the semiconductor chip are set in contact with corresponding electrodes with the semiconductor chip held in the holding section in the board body. Clamping mechanisms are located on the surface of the board body in the neighborhood of the holding section. The clamping mechanisms press the semiconductor chip held in the holding section. The respective bumps on the semiconductor chip are pressure contacted with the corresponding electrodes. Since the respective bumps are pressure contacted with the corresponding electrodes without using a solder, the respective bumps can be formed of an eutectic solder. The semiconductor chip held in the holding section can readily be taken out of the holding section by opening the clamping mechanisms.

摘要翻译： 构成特征评估板的板体具有用于将半导体芯片保持在其中的保持部。 半导体芯片具有多个凸块。 将半导体芯片的各个凸起设置成与半导体芯片保持在板体中的保持部中的相应电极接触。 夹持机构位于保持部附近的板体的表面。 夹持机构按压保持在保持部中的半导体芯片。 半导体芯片上的各个凸起与相应的电极压力接触。 由于各个凸块在不使用焊料的情况下与对应的电极进行压力接触，所以各凸点可以由共晶焊料形成。 通过打开夹持机构，保持在保持部分中的半导体芯片可以容易地从保持部分中取出。

公开(公告)号：US5747881A

公开(公告)日：1998-05-05

申请号：US593622

申请日：1996-01-30

申请人： Eiichi Hosomi ,  Hiroshi Tazawa ,  Chiaki Takubo ,  Koji Shibasaki

发明人： Eiichi Hosomi ,  Hiroshi Tazawa ,  Chiaki Takubo ,  Koji Shibasaki

IPC分类号： H01L21/60 ,  H01L21/603 ,  H01L23/495 ,  H01L23/50 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49572 ,  H01L23/49582 ,  H01L2224/05027 ,  H01L2224/05572 ,  H01L2924/0002 ,  H01L2924/01322

摘要： A semiconductor device comprises a semiconductor chip, an Au bump formed on the semiconductor chip, and Cu lead bonded to the Au bump through a bonding part. The Cu lead has a Cu core and a plated Sn layer formed on the Cu core, and the bonding part is formed of an Au--rich Au--Cu--Sn alloy of a ternary system having a single-phase structure with a composition of 15 atomic % Sn or less and 25 atomic % Cu or less.

摘要翻译： 半导体器件包括半导体芯片，形成在半导体芯片上的Au凸块，以及通过接合部分接合到Au凸块的Cu引线。 Cu引线具有在Cu芯上形成的Cu芯和镀Sn Sn，并且接合部由具有组成为15的单相结构的三元体系的富Au Au-Cu-Sn合金形成 原子％Sn以下且25原子％以下的Cu以下。

公开(公告)号：US5712493A

公开(公告)日：1998-01-27

申请号：US617241

申请日：1996-03-18

申请人： Miki Mori ,  Chiaki Takubo ,  Takeshi Sasaki

发明人： Miki Mori ,  Chiaki Takubo ,  Takeshi Sasaki

IPC分类号： G02F1/1345 ,  G02F1/13 ,  G09F9/00 ,  H01L21/60 ,  H01L23/538 ,  G02F1/1343 ,  G02F1/133 ,  G02F1/137 ,  H01L29/04

CPC分类号： G02F1/13452 ,  H01L23/5387 ,  H01L2924/0002

摘要： A display device comprising a substrate, a rectangular display section provided on the substrate and having four sides, a plurality of driving semiconductor elements formed on peripheral portions of the substrate in the vicinity of the display section, each of the driving semiconductor elements having two opposite long sides and two opposite short sides, one of the two long sides being opposed to one side of the display section, a plurality of output lines extending from the one long side of each of the driving semiconductor elements to the display section, to output signals from the driving semiconductor elements to the display section, a plurality of input lines extending from both the short sides of each of the driving semiconductor elements, to input signals to the driving semiconductor elements to drive them, a plurality of output terminals formed on each of the driving semiconductor elements along both the long sides thereof, and electrically connected to the output lines, the number of the output terminals located along one of the long sides being substantially equal to the number of the output terminals located along the other long side, and a plurality of input terminals formed on each of the driving semiconductor elements along both the short sides thereof, and electrically connected to the input lines.

摘要翻译： 一种显示装置，包括基板，设置在所述基板上的具有四个侧面的矩形显示部分，在所述显示部分附近形成在所述基板的周边部分上的多个驱动半导体元件，每个所述驱动半导体元件具有两个相对的 长边和两个相对的短边，两个长边中的一个与显示部分的一侧相对，多个输出线从每个驱动半导体元件的一个长边延伸到显示部分，以输出信号 从驱动半导体元件到显示部分，从驱动半导体元件的两个短边延伸的多条输入线输入到驱动半导体元件以驱动它们，多个输出端子形成在 驱动半导体元件沿着其两个长边并且电连接到输出线，nu 沿着一个长边位置的输出端子的mber基本上等于沿着另一个长边位置的输出端子的数量，以及沿其两个短边形成在每个驱动半导体元件上的多个输入端子， 并电连接到输入线。

公开(公告)号：US5631499A

公开(公告)日：1997-05-20

申请号：US656902

申请日：1996-06-03

申请人： Eiichi Hosomi ,  Chiaki Takubo ,  Hiroshi Tazawa ,  Ryouichi Miyamoto ,  Takashi Arai ,  Koji Shibasaki

发明人： Eiichi Hosomi ,  Chiaki Takubo ,  Hiroshi Tazawa ,  Ryouichi Miyamoto ,  Takashi Arai ,  Koji Shibasaki

IPC分类号： H01L21/28 ,  H01L21/321 ,  H01L21/60 ,  H01L23/485 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/14

摘要： A semiconductor device having a bump electrode includes a first conductive layer formed on a predetermined portion of a substrate. An insulating layer is formed on the substrate and the first conductive layer. The insulating layer has an opening portion such that a predetermined portion of the first conductive layer is exposed. A second conductive layer is formed on the first conductive layer, a side wall of the opening portion of the insulating layer, and an upper surface of the insulating layer. A third conductive layer is formed to cover at least the insulating layer on the first conductive layer and the second conductive layer along the portion. A fourth conductive layer is formed on the third conductive layer to have an over hang portion. A side etch portion is formed surrounded with an over hang portion of the fourth conductive layer, the third conductive layer, and the insulating layer.

摘要翻译： 具有凸块电极的半导体器件包括形成在基板的预定部分上的第一导电层。 在基板和第一导电层上形成绝缘层。 绝缘层具有使得第一导电层的预定部分露出的开口部。 在第一导电层，绝缘层的开口部分的侧壁和绝缘层的上表面上形成第二导电层。 形成第三导电层以至少覆盖沿着该部分的第一导电层和第二导电层上的绝缘层。 在第三导电层上形成第四导电层以具有过悬挂部分。 侧蚀刻部分形成为由第四导电层，第三导电层和绝缘层的悬垂部分围绕。