公开(公告)号：US07608479B2

公开(公告)日：2009-10-27

申请号：US11332262

申请日：2006-01-17

Applicant: Hirohisa Nakayama ,  Shiro Sato ,  Masanobu Shoji ,  Hitoshi Nosaka

Inventor： Hirohisa Nakayama ,  Shiro Sato ,  Masanobu Shoji ,  Hitoshi Nosaka

IPC: H01L21/00

CPC classification number: H05K3/3489 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02166 ,  H01L2224/02331 ,  H01L2224/0236 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0381 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/06131 ,  H01L2224/06155 ,  H01L2224/11 ,  H01L2224/1191 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2924/00 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014

Abstract: A method of manufacturing a semiconductor device includes: applying a paste containing acid to an electrical connection section which is electrically connected with a semiconductor substrate; removing the paste from the electrical connection section by washing the electrical connection section; and providing a conductive material to the electrical connection section.

Abstract translation: 一种制造半导体器件的方法包括：将含有酸的膏体施加到与半导体衬底电连接的电连接部分; 通过洗涤电连接部分从电连接部分去除糊料; 以及向所述电连接部提供导电材料。

公开(公告)号：US20090218685A1

公开(公告)日：2009-09-03

申请号：US12392312

申请日：2009-02-25

Applicant: Akihito NARITA ,  Naoya SATO

Inventor： Akihito NARITA ,  Naoya SATO

IPC: H01L23/48 ,  H01L21/603

CPC classification number: H01L24/16 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/3512

Abstract: A semiconductor module including: a semiconductor chip in which an integrated circuit is formed; an electrode formed on the semiconductor chip and electrically connected to the integrated circuit; an insulating film formed on the semiconductor chip and having an opening positioned corresponding to the electrode; an elastic protrusion disposed on the insulating film, a surface of the elastic protrusion opposite to the insulating film being convexly curved; an interconnect extending from over the electrode to over the elastic protrusion; an elastic substrate on which a lead is formed, the lead being in contact with part of the interconnect positioned on the elastic protrusion; and an adhesive maintaining a space between a surface of the semiconductor chip on which the elastic protrusion is formed and a surface of the elastic substrate on which the lead is formed. The elastic substrate has a first depression formed by elastic deformation. The lead is in contact with the interconnect on a surface of the first depression.

Abstract translation: 一种半导体模块，包括：形成集成电路的半导体芯片; 形成在所述半导体芯片上并电连接到所述集成电路的电极; 形成在所述半导体芯片上并具有对应于所述电极的开口的绝缘膜; 设置在所述绝缘膜上的弹性突起，与所述绝缘膜相对的所述弹性突起的表面凸出地弯曲; 从所述电极上方延伸到所述弹性突起上方的互连; 弹性基板，其上形成有引线，所述引线与布置在所述弹性突起上的所述互连部分接触; 以及在其上形成有弹性突起的半导体芯片的表面与形成有引线的弹性基板的表面之间保持空间的粘合剂。 弹性基板具有通过弹性变形形成的第一凹部。 引线与第一凹陷表面上的互连件接触。

公开(公告)号：US07521796B2

公开(公告)日：2009-04-21

申请号：US11480846

申请日：2006-07-06

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L23/48

CPC classification number: H01L24/11 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/36 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device with a package size close to its chip size is, apart from a stress absorbing layer, such as to effectively absorb thermal stresses. A semiconductor device (150) has a semiconductor chip provided with electrodes (158), a resin layer (152) forming a stress relieving layer provided on the semiconductor chip, wiring (154) formed from the electrodes (158) to over the resin layer (152), and solder balls (157) formed on the wiring (154) over the resin layer (152); the resin layer (152) is formed so as to have a depression (152a) in the surface, and the wiring (154) is formed so as to pass over the depression (152a).

Abstract translation: 具有接近其芯片尺寸的封装尺寸的半导体器件除了应力吸收层之外还有效地吸收热应力。 半导体器件（150）具有设置有电极（158）的半导体芯片，形成在半导体芯片上的应力消除层的树脂层（152），由电极（158）形成在树脂层上方的布线（154） （152）和形成在所述布线（154）上的所述树脂层（152）上的焊球（157）; 树脂层（152）形成为在表面上具有凹部（152a），并且布线（154）形成为越过凹部（152a）。

公开(公告)号：US20080145973A1

公开(公告)日：2008-06-19

申请号：US12007406

申请日：2008-01-10

Applicant: Takehiko Murakami

Inventor： Takehiko Murakami

IPC: H01L21/60

CPC classification number: H01L23/3114 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0332 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/1132 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2224/05552 ,  H01L2924/00

Abstract: To widely improve an entire manufacturing efficiency by efficiently forming a thermal stress relaxing post, an insulating layer and a solder bump, a rewiring circuit (3) is formed on a wafer (1) by plating, a thermal stress relaxing post (4) made of a conductive material such as a solder or the like is formed on the rewiring circuit (3), an insulating layer (6) made of a polyimide or the like is formed in the periphery of the rewiring circuit (3) and the thermal stress relaxing post (4) except a top surface of the thermal stress relaxing post (4), a solder bump (7) is formed on the thermal stress relaxing post (4), and the thermal stress relaxing post (4), the insulating layer (6) and the solder bump (7) are formed by screen printing.

Abstract translation: 为了通过有效地形成热应力放松柱，绝缘层和焊料凸块来广泛提高整体制造效率，通过电镀在晶片（1）上形成再布线电路（3），制成热应力放松柱（4） 在重新配线电路（3）上形成诸如焊料等的导电材料，在重新布线电路（3）的周围形成由聚酰亚胺等构成的绝缘层（6），并且热应力 除了热应力松弛柱（4）的上表面之外，在热应力松弛柱（4）和热应力松弛柱（4）之间形成焊料凸点（7），绝缘层 （6）和焊料凸块（7）通过丝网印刷形成。

公开(公告)号：US20080119037A1

公开(公告)日：2008-05-22

申请号：US11942809

申请日：2007-11-20

Applicant: Yasunori KUROSAWA

Inventor： Yasunori KUROSAWA

IPC: H01L21/44

CPC classification number: H01L23/3114 ,  H01L21/6835 ,  H01L23/3157 ,  H01L24/11 ,  H01L24/12 ,  H01L24/27 ,  H01L24/94 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/1131 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14

Abstract: A method for manufacturing a semiconductor device includes: (a) forming a stress relaxation layer on a first surface having an electrode of a semiconductor substrate; (b) forming a wiring line so as to cover the electrode and the stress relaxation layer after step (a); (c) forming a solder resist layer on the wiring line after step (b); and (d) forming a protective layer on a second surface opposite to the first surface of the semiconductor substrate after step (c).

Abstract translation: 一种制造半导体器件的方法包括：（a）在具有半导体衬底的电极的第一表面上形成应力松弛层; （b）在步骤（a）之后形成布线以覆盖电极和应力松弛层; （c）在步骤（b）之后在布线上形成阻焊层; 和（d）在步骤（c）之后在与半导体衬底的第一表面相对的第二表面上形成保护层。

公开(公告)号：US20080067663A1

公开(公告)日：2008-03-20

申请号：US11522885

申请日：2006-09-18

Applicant: Teck-Gyu Kang ,  Belgacem Haba ,  Guilian Gao

Inventor： Teck-Gyu Kang ,  Belgacem Haba ,  Guilian Gao

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/81 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/11334 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2224/29099

Abstract: Wafer level chip packages including risers having sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies.

Abstract translation: 公开了包括具有倾斜侧壁的立管和制造这种芯片封装的方法的晶片级芯片封装。 本发明的晶片级芯片封装可有利地用于各种微电子组件中。

公开(公告)号：US07169647B2

公开(公告)日：2007-01-30

申请号：US10842259

申请日：2004-05-07

Applicant: Octavio Trovarelli ,  Ingo Uhlendorf ,  David Wallis ,  Axel Brintzinger

Inventor： Octavio Trovarelli ,  Ingo Uhlendorf ,  David Wallis ,  Axel Brintzinger

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/0236 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05016 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155

Abstract: A conductive connection is made between a semiconductor chip and an external conductor structure. An elevation element is applied on the surface of the semiconductor chip and a soldering island is arranged on the elevation element. An interconnect is produced below the soldering island as far as a bonding island or an I/O pad. Increased reliability of conductive connections of the bonding island or the I/O pad to an external conductive structure can be achieved by preventing the flowing-away of the solder and the oxidation or corrosion of the conductive layer.

Abstract translation: 在半导体芯片和外部导体结构之间形成导电连接。 在半导体芯片的表面上施加高度元件，在升降元件上设置焊接岛。 在焊岛下方产生互连，只要接合岛或I / O焊盘即可。 可以通过防止焊料的流失和导电层的氧化或腐蚀来实现将接合岛或I / O焊盘与外部导电结构的导电连接的可靠性提高。

公开(公告)号：US07132749B2

公开(公告)日：2006-11-07

申请号：US11099255

申请日：2005-04-05

Applicant: Haruki Ito

Inventor： Haruki Ito

IPC: H01L23/48

CPC classification number: H01L24/14 ,  G02F1/13458 ,  H01L21/4846 ,  H01L23/485 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0236 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/114 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1161 ,  H01L2224/11622 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13008 ,  H01L2224/13013 ,  H01L2224/13018 ,  H01L2224/1319 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13666 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device is provided with a plurality of protrusions which are made of a resin and which protrude higher than electrodes, and conductive layers which are electrically connected to the electrodes and which cover the top surfaces of the protrusions. A method for manufacturing the semiconductor device includes a step of applying a layer of the resin to the semiconductor device except for the electrodes, a step of patterning the conductive layers on the electrodes and the layer of the resin in accordance with the protrusions, and a step of removing the layer of the resin located between the conductive layers by the use of the patterned conductive layers as masks so as to form the protrusions.

Abstract translation: 半导体器件具有多个由树脂制成并且高于电极的突起，以及与电极电连接并覆盖突起的顶表面的导电层。 一种半导体器件的制造方法，其特征在于，除了电极以外，还具有对半导体装置施加一层树脂的工序，根据突起对电极上的导电层和树脂层进行图案化的工序， 通过使用图案化的导电层作为掩模去除位于导电层之间的树脂层以形成突起的步骤。

公开(公告)号：US20060237836A1

公开(公告)日：2006-10-26

申请号：US11474199

申请日：2006-06-23

Applicant: Joseph Fjelstad ,  Konstantine Karavakis

Inventor： Joseph Fjelstad ,  Konstantine Karavakis

IPC: H01L23/52

CPC classification number: H01L23/3114 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/498 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/72 ,  H01L24/82 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/85424 ,  H01L2924/00011 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2924/01004

Abstract: A compliant semiconductor chip package assembly includes a a semiconductor chip having a plurality of chip contacts, and a compliant layer having a top surface, a bottom surface and sloping peripheral edges, whereby the bottom surface of the compliant layer overlies a surface of the semiconductor chip. The assembly also includes a plurality of electrically conductive traces connected to the chip contacts of the semiconductor chip, the traces extending along the sloping edges to the top surface of the compliant layer. The assembly may include conductive terminals overlying the semiconductor chip, with the compliant layer supporting the conductive terminals over the semiconductor chip. The conductive traces have first ends electrically connected with the contacts of the semiconductor chip and second ends electrically connected with the conductive terminals. The conductive terminals are movable relative to the semiconductor chip.

Abstract translation: 兼容的半导体芯片封装组件包括具有多个芯片触点的半导体芯片和具有顶表面，底表面和倾斜周边边缘的柔性层，由此柔性层的底表面覆盖在半导体芯片的表面上。 组件还包括连接到半导体芯片的芯片触点的多个导电迹线，迹线沿倾斜边缘延伸到柔性层的顶表面。 组件可以包括覆盖半导体芯片的导电端子，其中柔性层将导电端子支撑在半导体芯片上。 导电迹线具有与半导体芯片的触点电连接的第一端和与导电端子电连接的第二端。 导电端子可相对于半导体芯片移动。

公开(公告)号：US20040145031A1

公开(公告)日：2004-07-29

申请号：US10726275

申请日：2003-12-02

Inventor： Haruki Ito

IPC: H01L021/4763 ,  H01L023/58 ,  H01L029/40 ,  H01L023/48

CPC classification number: H01L24/14 ,  G02F1/13458 ,  H01L21/4846 ,  H01L23/485 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0236 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/114 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1161 ,  H01L2224/11622 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13008 ,  H01L2224/13013 ,  H01L2224/13018 ,  H01L2224/1319 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13666 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device is provided with a plurality of protrusions which are made of a resin and which protrude higher than electrodes, and conductive layers which are electrically connected to the electrodes and which cover the top surfaces of the protrusions. A method for manufacturing the semiconductor device includes a step of applying a layer of the resin to the semiconductor device except for the electrodes, a step of patterning the conductive layers on the electrodes and the layer of the resin in accordance with the protrusions, and a step of removing the layer of the resin located between the conductive layers by the use of the patterned conductive layers as masks so as to form the protrusions.

Abstract translation: 半导体器件具有多个由树脂制成并且高于电极的突起，以及与电极电连接并覆盖突起的顶表面的导电层。 一种半导体器件的制造方法，其特征在于，除了电极以外，还具有对半导体装置施加一层树脂的工序，根据突起对电极上的导电层和树脂层进行图案化的工序， 通过使用图案化的导电层作为掩模去除位于导电层之间的树脂层以形成突起的步骤。