利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

24 条记录 (耗时 0.015 秒)

    Method and/or apparatus implemented in hardware to discard bad logical transmission units (LTUs)
    2.
    发明授权
    Method and/or apparatus implemented in hardware to discard bad logical transmission units (LTUs) 有权
    在硬件中实现的丢弃不良逻辑传输单元（LTU）的方法和/或装置

    公开(公告)号：US07340667B2

    公开(公告)日：2008-03-04

    申请号：US10842376

    申请日：2004-05-10

    申请人： Alon Saado ,  Muhammad Afsar

    发明人： Alon Saado ,  Muhammad Afsar

    IPC分类号： H03M13/00

    CPC分类号： H04L1/0052 ,  H04L1/0061

    摘要： The present invention concerns an apparatus comprising a logic circuit, a compare circuit, a control circuit and a memory interface. The logic circuit may be configured to generate a check signal in response to (i) a data signal having a series of logical transmission units (LTUs) and (ii) a first control signal. The compare circuit may be configured to generate a compare signal in response to the check signal and the data signal. The control circuit configured to generate (i) the first control signal and (ii) a second control signal indicating a valid or invalid status of each of the LTUs, in response to a data valid signal and the compare signal. The memory interface may be configured to generate an output data signal in response to the second control signal. The memory interface is generally configured to store only the LTUs having a valid status.

    摘要翻译： 本发明涉及一种包括逻辑电路，比较电路，控制电路和存储器接口的装置。 逻辑电路可以被配置为响应于（i）具有一系列逻辑传输单元（LTU）的数据信号和（ii）第一控制信号而产生检查信号。 比较电路可以被配置为响应于检查信号和数据信号而产生比较信号。 所述控制电路经配置以响应于数据有效信号和所述比较信号产生（i）所述第一控制信号和（ii）指示每个所述LTU的有效或无效状态的第二控制信号。 存储器接口可以被配置为响应于第二控制信号而产生输出数据信号。 存储器接口通常被配置为仅存储具有有效状态的LTU。

    Method and/or apparatus implemented in hardware to discard bad logical transmission units (LTUs)
    3.
    发明申请
    Method and/or apparatus implemented in hardware to discard bad logical transmission units (LTUs) 有权
    在硬件中实现的丢弃不良逻辑传输单元（LTU）的方法和/或装置

    公开(公告)号：US20050251717A1

    公开(公告)日：2005-11-10

    申请号：US10842376

    申请日：2004-05-10

    申请人： Alon Saado ,  Muhammad Afsar

    发明人： Alon Saado ,  Muhammad Afsar

    IPC分类号： G01R31/28 ,  G06F11/00 ,  H03M13/00 ,  H04L1/00 ,  H04L1/20

    CPC分类号： H04L1/0052 ,  H04L1/0061

    摘要： The present invention concerns an apparatus comprising a logic circuit, a compare circuit, a control circuit and a memory interface. The logic circuit may be configured to generate a check signal in response to (i) a data signal having a series of logical transmission units (LTUs) and (ii) a first control signal. The compare circuit may be configured to generate a compare signal in response to the check signal and the data signal. The control circuit configured to generate (i) the first control signal and (ii) a second control signal indicating a valid or invalid status of each of the LTUs, in response to a data valid signal and the compare signal. The memory interface may be configured to generate an output data signal in response to the second control signal. The memory interface is generally configured to store only the LTUs having a valid status.

    摘要翻译： 本发明涉及包括逻辑电路，比较电路，控制电路和存储器接口的装置。 逻辑电路可以被配置为响应于（i）具有一系列逻辑传输单元（LTU）的数据信号和（ii）第一控制信号而产生检查信号。 比较电路可以被配置为响应于检查信号和数据信号而产生比较信号。 所述控制电路经配置以响应于数据有效信号和所述比较信号产生（i）所述第一控制信号和（ii）指示每个所述LTU的有效或无效状态的第二控制信号。 存储器接口可以被配置为响应于第二控制信号而产生输出数据信号。 存储器接口通常被配置为仅存储具有有效状态的LTU。

    Method and/or apparatus for generating a write gated clock signal
    4.
    发明授权
    Method and/or apparatus for generating a write gated clock signal 有权
    用于产生写门控时钟信号的方法和/或装置

    公开(公告)号：US07046066B2

    公开(公告)日：2006-05-16

    申请号：US10867899

    申请日：2004-06-15

    申请人： Alon Saado ,  Linley M. Young ,  Muhammad Afsar

    发明人： Alon Saado ,  Linley M. Young ,  Muhammad Afsar

    IPC分类号： G06F1/04

    CPC分类号： G06F1/32 ,  G06F1/10 ,  G11C2029/3202

    摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a gated clock signal in response to (i) a write enable signal and (ii) a system clock signal. The gated clock signal is pulsed active while the write enable signal is active. The second circuit may be configured to generate the write enable signal.

    摘要翻译： 一种包括第一电路和第二电路的装置。 第一电路可以被配置为响应于（i）写使能信号和（ii）系统时钟信号而产生门控时钟信号。 当写使能信号有效时，门控时钟信号是脉冲激活的。 第二电路可以被配置为产生写使能信号。

    Circuit and method for patching for program ROM
    5.
    发明授权
    Circuit and method for patching for program ROM 有权
    用于程序ROM修补的电路和方法

    公开(公告)号：US07644223B2

    公开(公告)日：2010-01-05

    申请号：US11589355

    申请日：2006-10-30

    申请人： Alon Saado

    发明人： Alon Saado

    IPC分类号： G06F12/02 ,  G06F12/06

    CPC分类号： G11C7/1006 ,  G06F9/322 ,  G06F9/328 ,  G11C29/822 ,  G11C29/846 ,  G11C2207/104

    摘要： This invention discloses a system comprising a first comparator circuit configured to assert a first control signal in response to a first input number matching one of a first numbers stored therein, a second comparator circuit configured to assert a second control signal in response to: (i) at least one latched assertion of the first control signal; (ii) a second input number matching an intermediate number produced by incrementing the first input number; and (iii) an assertion of an input signal, and to de-assert the second control signal absent of either the matching between the second input number and the intermediate number or the de-assertion of the input signal, and a generator circuit configured to output a predetermined instruction data stored therein in response to the assertion of the first control signal, and to output a third number in response to the assertions of the second control signal.

    摘要翻译： 本发明公开了一种系统，包括：第一比较器电路，被配置为响应于与其中存储的第一数字匹配的第一输入数字来声明第一控制信号;第二比较器电路，被配置为响应于：（i ）所述第一控制信号的至少一个锁存断言; （ii）与通过递增第一输入数而产生的中间数相匹配的第二输入数; 以及（iii）输入信号的断言，并且去除所述第二控制信号，所述第二控制信号不存在所述第二输入号码与所述中间号码之间的匹配或所述输入信号的所述取消断言;以及发生器电路， 响应于第一控制信号的断言输出存储在其中的预定指令数据，并且响应于第二控制信号的断言输出第三数字。

    Centralized recording and processing of received packet parameters
    6.
    发明授权
    Centralized recording and processing of received packet parameters 失效
    集中记录和处理接收到的数据包参数

    公开(公告)号：US08681786B2

    公开(公告)日：2014-03-25

    申请号：US12701694

    申请日：2010-02-08

    申请人： Qiang Shen ,  Tarun Tandon ,  Alon Saado

    发明人： Qiang Shen ,  Tarun Tandon ,  Alon Saado

    IPC分类号： H04L12/56

    CPC分类号： H04L1/1812 ,  H04L1/0072 ,  H04L1/0075 ,  H04L1/0083

    摘要： The invention relates to an internet application flow rate identification method based on message sampling and application signing, comprising the following steps: firstly, message sampling capture: in accordance with sampling strategy and sampling rate the message is captured and decoded; secondly, decoding: the flow information and application data of the message is analyzed by decoding the message; thirdly, flow classification: according to the flow information of the message, a flow state table is found and maintained; fourthly, flow state distinguishing: the signature is matched if the application type of the flow state found through the flow classification is unknown; finally, signature matching: according to the application signature bank, the application data of the message is matched, if matched successfully, the application type of the flow state is updated, and the flow information and application type of that data stream is output. The method is of high accuracy in identification, high efficiency in processing, good expandability, high possibility in realization, and is applicable not only for message processing, but also for flow data analysis. The invention can be achieved in not only the network equipment, but also the network analysis system.

    摘要翻译： 本发明涉及基于消息采样和应用签名的互联网应用流量识别方法，包括以下步骤：首先，消息采样捕获：根据采样策略和采样率，消息被捕获和解码; 其次，解码：通过解码消息来分析消息的流信息和应用数据; 第三，流分类：根据消息的流程信息，发现并维护流状态表; 第四，流状态区分：如果通过流分类发现的流状态的应用类型未知，则签名匹配; 最后，签名匹配：根据应用签名库，消息的应用数据匹配，如果匹配成功，则更新流状态的应用类型，并输出该数据流的流信息和应用类型。 该方法识别精度高，处理效率高，扩展性好，实现可能性高，不仅适用于消息处理，而且适用于流量数据分析。 本发明不仅可以实现网络设备，而且可以实现网络分析系统。

    Method and/or apparatus for performing static timing analysis on a chip in scan mode with multiple scan clocks
    7.
    发明授权
    Method and/or apparatus for performing static timing analysis on a chip in scan mode with multiple scan clocks 有权
    用于以具有多个扫描时钟的扫描模式在芯片上执行静态时序分析的方法和/或装置

    公开(公告)号：US07231567B2

    公开(公告)日：2007-06-12

    申请号：US10789883

    申请日：2004-02-27

    申请人： Alon Saado ,  Linley Young

    发明人： Alon Saado ,  Linley Young

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318594

    摘要： An apparatus comprising a circuit configured to be tested and a plurality of test blocks within the circuit. Each of the test blocks generally comprises (i) a plurality of sequential elements and (ii) a plurality of logic elements. Each of the test blocks are configured to operate (a) in a first mode comprising a shift mode and (b) a second mode comprising a capture mode. The shift mode generally operates with multiple scan clocks that are clocked simultaneously. The capture mode generally operates with multiple scan clocks, but only one of which is toggled at a time.

    摘要翻译： 一种包括被配置为被测试的电路和该电路内的多个测试块的设备。 每个测试块通常包括（i）多个顺序元件和（ii）多个逻辑元件。 每个测试块被配置为在包括移位模式的第一模式中操作（a）和（b）包括捕获模式的第二模式。 移位模式通常以同时计时的多个扫描时钟进行操作。 捕获模式通常以多个扫描时钟进行操作，但一次只能切换其中一个。

    CENTRALIZED RECORDING AND PROCESSING OF RECEIVED PACKET PARAMETERS
    9.
    发明申请
    CENTRALIZED RECORDING AND PROCESSING OF RECEIVED PACKET PARAMETERS 失效
    接收到的分组参数的集中记录和处理

    公开(公告)号：US20110194555A1

    公开(公告)日：2011-08-11

    申请号：US12701694

    申请日：2010-02-08

    申请人： Qiang Shen ,  Tarun Tandon ,  Alon Saado

    发明人： Qiang Shen ,  Tarun Tandon ,  Alon Saado

    IPC分类号： H04L12/56

    CPC分类号： H04L1/1812 ,  H04L1/0072 ,  H04L1/0075 ,  H04L1/0083

    摘要： A receiver for maintaining parameters of packets received from a transmitter is provided. In the receiver: a first module receives packets from the transmitter and decodes the packets to obtain corresponding payload data, wherein each received packet is transmitted in accordance with a first set of parameters predetermined before decoding of the packets, a second set of parameters which are dynamically determined when the packets are being decoded, and a third set of parameters which are determined after the packets have been decoded. Also, a record generating module generates a record for each received packet, wherein the record comprises the first set, the second set, and the third set of parameters and a buffering module stores the record and corresponding payload data of each received packet. A second module retrieves the record and corresponding payload data from the buffering module, and processes the corresponding payload data according to the record.

    摘要翻译： 提供了一种用于维护从发射机接收的分组的参数的接收机。 在接收机中：第一模块从发射机接收分组并对分组进行解码以获得相应的有效载荷数据，其中根据分组解码之前预先确定的第一组参数来传输每个接收到的分组，第二组参数是 在分组被解码时动态地确定，以及在分组被解码之后确定的第三组参数。 此外，记录生成模块为每个接收到的分组生成记录，其中记录包括第一组，第二组和第三组参数，并且缓冲模块存储每个接收分组的记录和对应的有效载荷数据。 第二模块从缓冲模块检索记录和对应的有效载荷数据，并根据记录处理相应的有效载荷数据。

    Canonical signed digit (CSD) coefficient multiplier with optimization
    10.
    发明授权
    Canonical signed digit (CSD) coefficient multiplier with optimization 失效
    经典有符号数（CSD）系数乘法器与优化

    公开(公告)号：US07680872B2

    公开(公告)日：2010-03-16

    申请号：US11032920

    申请日：2005-01-11

    申请人： Alon Saado

    发明人： Alon Saado

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5332 ,  G06F7/5443 ,  H03H17/0226 ,  H03H2017/0232

    摘要： An apparatus comprising an address generation circuit, a lookup table, a multiplexer and an output circuit. The address generation circuit may be configured to generate a series of addresses. The lookup table may be configured to generate one or more coefficients in response to the addresses. The multiplexer circuit may be configured to generate one or more shifted values in response to (i) the coefficients and (ii) the one or more operands. The output circuit may be configured to generate an output signal by combining one or more component values in response to said shifted values. The coefficients are grouped as one over power of 2 components into mutually exclusive groups.

    摘要翻译： 一种包括地址生成电路，查找表，多路复用器和输出电路的装置。 地址生成电路可以被配置为生成一系列地址。 查找表可以被配置为响应于地址生成一个或多个系数。 多路复用器电路可以被配置为响应于（i）系数和（ii）一个或多个操作数而产生一个或多个移位值。 输出电路可以被配置为通过响应于所述偏移值组合一个或多个分量值来产生输出信号。 这些系数被分组为2个分量的功率作为互斥组。