公开(公告)号：US5374344A

公开(公告)日：1994-12-20

申请号：US97810

申请日：1993-07-27

申请人： Thomas P. Gall ,  James Wilcox

发明人： Thomas P. Gall ,  James Wilcox

IPC分类号： H05K3/24 ,  C25D5/02 ,  C25D5/12

CPC分类号： H05K3/241

摘要： Disclosed is a multi-compartment electroplating tank and a process for using the tank to simultaneously plate dissimilar materials onto a substrate.

摘要翻译： 公开了一种多室电镀槽和使用该罐同时将不同材料平板地放置在基板上的工艺。

公开(公告)号：US5403420A

公开(公告)日：1995-04-04

申请号：US97603

申请日：1993-07-27

申请人： Thomas P. Gall ,  James R. Loomis ,  David B. Stone ,  Cheryl L. Tytran ,  James Wilcox

发明人： Thomas P. Gall ,  James R. Loomis ,  David B. Stone ,  Cheryl L. Tytran ,  James Wilcox

IPC分类号： G11C5/00 ,  H05K3/00 ,  H05K3/46 ,  B32B31/00

CPC分类号： H05K3/462 ,  B32B37/1207 ,  B32B2327/12 ,  B32B2379/00 ,  B32B2457/00 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09536 ,  H05K2203/068 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4691 ,  Y10T29/49105

摘要： Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate.

摘要翻译： 公开了一种并行处理器封装结构和用于制造该结构的方法。 单独的逻辑和存储器元件在印刷电路卡上。 这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。 通过在层压板中实现的开关结构来提供互通。 印刷电路卡安装在或连接到多个电路化的柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。 电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。 该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上，并且通过Z轴与其它柔性层通信， 轴向电路（通孔和通孔）。

公开(公告)号：US07353983B2

公开(公告)日：2008-04-08

申请号：US10695187

申请日：2003-10-28

申请人： William C. Weigler ,  Robert Babula ,  James E. Herbold ,  Thomas P. Gall ,  Steven G. Sharkey

发明人： William C. Weigler ,  Robert Babula ,  James E. Herbold ,  Thomas P. Gall ,  Steven G. Sharkey

IPC分类号： B23K1/018

CPC分类号： H05K3/3457 ,  B23K1/018 ,  B23K2101/42 ,  H01L24/11 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/0101 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K3/42 ,  H05K2201/10204 ,  H05K2203/046 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method for vertical removal of excess solder from a circuit substrate includes the use of a sacrificial circuit substrate with a plurality of pads and vias that are solder-wettable. The pads and vias of the sacrificial circuit substrate are placed in vertical proximity to the excess solder of the circuit substrate. The excess solder is heated until it is liquid, wherein the excess solder is wicked vertically onto the pads and into the vias of the sacrificial circuit substrate. Thereafter, the sacrificial circuit substrate is lifted from the proximity of the circuit substrate while the solder is in a liquid, taking the excess solder with it but leaving a predetermined amount on the circuit substrate.

摘要翻译： 用于从电路基板垂直去除多余焊料的方法包括使用具有可焊接润湿的多个焊盘和通孔的牺牲电路基板。 牺牲电路衬底的焊盘和通孔被放置成垂直靠近电路衬底的多余焊料。 多余的焊料被加热直到它是液体，其中多余的焊料被垂直地焊接到焊盘上并进入牺牲电路衬底的通孔中。 此后，牺牲电路基板从电路基板的附近被提起，同时焊料处于液体中，取出多余的焊料，但在电路基板上留下预定的量。

公开(公告)号：US07570492B2

公开(公告)日：2009-08-04

申请号：US10801515

申请日：2004-03-16

申请人： Thomas P. Gall ,  Michael Pfeifer ,  Anthony Polak ,  Michael J. Pomeroy

发明人： Thomas P. Gall ,  Michael Pfeifer ,  Anthony Polak ,  Michael J. Pomeroy

IPC分类号： H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC分类号： H05K5/0047 ,  H05K1/0215 ,  H05K1/0272 ,  H05K3/0061 ,  H05K3/42 ,  H05K5/0213 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/09063 ,  H05K2201/096 ,  H05K2201/0999 ,  H05K2201/10666 ,  H05K2203/0191 ,  H05K2203/1178 ,  H05K2203/1394

摘要： An electronic control module comprising a vent assembly is provided. The electronic control module comprises a housing having a first aperture and a substrate disposed within the housing. The substrate has a second aperture positioned adjacent to the first aperture, and includes the hydrophobic vent assembly disposed over the second aperture and adheringly coupled to the substrate. The hydrophobic vent assembly may be adapted to prevent the ingress of moisture and permit the egress of certain gases.

摘要翻译： 提供一种包括通气口组件的电子控制模块。 电子控制模块包括具有第一孔和设置在壳体内的衬底的壳体。 衬底具有邻近第一孔定位的第二孔，并且包括设置在第二孔上方并附着于衬底的疏水排气组件。 疏水排气组件可以适于防止湿气进入并允许某些气体的排出。

公开(公告)号：US06749105B2

公开(公告)日：2004-06-15

申请号：US10103590

申请日：2002-03-21

申请人： Ying Wang ,  Thomas P. Gall

发明人： Ying Wang ,  Thomas P. Gall

IPC分类号： B23K120

CPC分类号： B23K1/0008 ,  B23K2101/04

摘要： A method for securing a metallic substrate (24) to a metallic housing (26). The method may include: firing a first solderable coating (64) to an edge (60) of the metallic substrate (24); firing a second solderable coating (64) to a groove (62) of the metallic housing (26); joining the edge (60) of the metallic substrate (24) to the groove (62) of the metallic housing (26) to form a joint (66) at the first solderable coating and the second solderable coating; applying a solder (68) to the joint (66); and solder bonding the metallic substrate (24) to the metallic housing (26) to provide a hermetic seal at the joint (66). There is also an electronic control module that incorporates the method.

摘要翻译： 一种用于将金属基底（24）固定到金属外壳（26）上的方法。 该方法可以包括：将第一可焊接涂层（64）烧制到金属基底（24）的边缘（60）上; 向所述金属壳体（26）的凹槽（62）烧制第二可焊接涂层（64）; 将金属基材（24）的边缘（60）接合到金属壳体（26）的凹槽（62），以在第一可焊接涂层和第二可焊接涂层处形成接头（66）; 将焊料（68）施加到接头（66）上; 并将所述金属基底（24）焊接到所述金属壳体（26）上以在所述接头（66）处提供气密密封。 还有一个并入该方法的电子控制模块。

公开(公告)号：US06483037B1

公开(公告)日：2002-11-19

申请号：US10008422

申请日：2001-11-13

申请人： Kevin D. Moore ,  Thomas P. Gall

发明人： Kevin D. Moore ,  Thomas P. Gall

IPC分类号： H05K109

CPC分类号： H05K3/4691 ,  H05K1/0278 ,  H05K1/0366 ,  H05K3/0061 ,  H05K3/28 ,  H05K2201/09109 ,  H05K2201/09745 ,  H05K2203/302 ,  Y10T29/49135

摘要： A flexible circuit (100) includes a first circuit path portion (110) and a second rigid circuit path portion (140) to which electronic components (102) may be coupled. Each circuit path portion (110 and 140) including a resin layer (112 and 142) and an adjacent conductive layer (114 and 144). Each circuit path portion (110 and 140) defining a gap (120 and 150) substantially running along a line corresponding to a desired bend location. A central circuit path portion (130) is disposed between the first circuit path portion (110) and the second rigid circuit path portion (140) and includes a first conductive layer (134) in electrical communication with the first circuit path portion (110) and a second conductive layer (136) in electrical communication with the second rigid circuit path portion (140), so as to provide electrical communication across the gaps (120 and 150). A metal plate (160) is disposed adjacent the second rigid circuit path portion (140).

摘要翻译： 柔性电路（100）包括第一电路路径部分（110）和第二刚性电路路径部分（140），电子部件（102）可以耦合到该第一电路路径部分。 每个电路路径部分（110和140）包括树脂层（112和142）和相邻的导电层（114和144）。 每个电路路径部分（110和140）限定基本上沿着对应于期望的弯曲位置的线行进的间隙（120和150）。 中心电路路径部分（130）设置在第一电路路径部分（110）和第二刚性电路路径部分（140）之间，并包括与第一电路路径部分（110）电连通的第一导电层（134） 以及与所述第二刚性电路路径部分（140）电连通的第二导电层（136），以便跨越所述间隙（120和150）提供电连通。 金属板（160）设置成邻近第二刚性电路路径部分（140）。

公开(公告)号：US5185073A

公开(公告)日：1993-02-09

申请号：US692606

申请日：1991-04-29

申请人： Perminder S. Bindra ,  Jerome J. Cuomo ,  Thomas P. Gall ,  Anthony P. Ingraham ,  Sung K. Kang ,  Jungihl Kim ,  Paul Lauro ,  David N. Light ,  Voya R. Markovich ,  Ekkehard F. Miersch ,  Jaynal A. Molla ,  Douglas O. Powell ,  John J. Ritsko ,  George J. Saxenmeyer, Jr. ,  Jack A. Varcoe ,  George F. Walker

发明人： Perminder S. Bindra ,  Jerome J. Cuomo ,  Thomas P. Gall ,  Anthony P. Ingraham ,  Sung K. Kang ,  Jungihl Kim ,  Paul Lauro ,  David N. Light ,  Voya R. Markovich ,  Ekkehard F. Miersch ,  Jaynal A. Molla ,  Douglas O. Powell ,  John J. Ritsko ,  George J. Saxenmeyer, Jr. ,  Jack A. Varcoe ,  George F. Walker

IPC分类号： H01R4/26 ,  H01R4/58 ,  H01R13/22 ,  H05K3/32

CPC分类号： H01L24/83 ,  H01L24/90 ,  H01R13/22 ,  H01R4/26 ,  H01R4/58 ,  H05K3/325 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/13111 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/48227 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14

摘要： A separable and reconnectable connection for electrical equipment is provided that is suitable for miniaturization in which vertical interdigitating members integrally attached and protruding from a planar portion are accommodated in control of damage in lateral displacement that occurs on mating with an opposite similar contact. Displacement damage is averted through accommodating lateral stresses by providing one or more of a conformal opposing contact, by strengthening through coating and base reinforcement and a deformable coating. The contacts are fabricated by physical and chemical processes including sputtering, normal and pulse electroplating and chemical vapor deposition. Pulse electroplating of palladium provides a dendritic deposit of uniform height, uniform rounded points and less branching. The contacts on completion are provided with a surrounding immobilizing material that enhances rigidity.

摘要翻译： 提供一种用于电气设备的可分离和可重新连接的连接件，其适于小型化，其中容纳从平面部分一体地附接和突出的垂直交叉构件，以控制与相对的类似接触件配合时发生的横向位移损坏。 通过提供一个或多个共形相对的接触，通过加强涂层和基底加强件以及可变形的涂层来容纳横向应力来避免位移损伤。 接触是通过物理和化学过程制造的，包括溅射，正常和脉冲电镀以及化学气相沉积。 钯的脉冲电镀提供均匀高度，均匀圆点和较少支化的树枝状沉积物。 完成的触点设置有增强刚性的周边固定材料。

公开(公告)号：US5709805A

公开(公告)日：1998-01-20

申请号：US755527

申请日：1996-11-20

申请人： Charles Robert Davis ,  Thomas P. Gall

发明人： Charles Robert Davis ,  Thomas P. Gall

IPC分类号： H05K1/05 ,  H05K3/00 ,  H05K3/30 ,  H05K3/38 ,  H05K3/42 ,  H05K3/44 ,  H05K3/46 ,  B44C1/22 ,  C23F1/00

CPC分类号： H05K3/445 ,  H05K3/386 ,  H05K3/4623 ,  H05K3/4641 ,  H05K1/056 ,  H05K2201/015 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/068 ,  H05K3/002 ,  H05K3/305 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4626 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/249982 ,  Y10T428/249984 ,  Y10T428/249986 ,  Y10T428/2804 ,  Y10T428/3154

摘要： A method for producing a panel of a multi-layer electronic circuit package and resulting article of manufacture is provided comprising the steps of coating a circuitized core material that has been cut into panels with a dielectric material and copper cover sheets; forming circuits from the cover sheets by etching; applying an adhesive polymer across the dielectric material covering the entire area of the panel; applying a cover sheet; drilling the panel to form through-holes and vias; seeding and plating the through-holes and vias with joining metal; applying photo-resist to the panels exposed with an image of the area of the panel to be joined and developed; and etching the cover sheet and the photo-resist away in the area of the panel to be joined to expose the adhesive polymer.

摘要翻译： 提供一种多层电子电路封装的面板的制造方法及其制造方法，其特征在于包括以下步骤：利用电介质材料和铜覆盖层将被切割成电路的芯材涂覆在板上; 通过蚀刻从覆盖片形成电路; 在覆盖面板的整个区域的电介质材料上施加粘合剂聚合物; 应用封面; 钻孔板形成通孔和通孔; 用连接金属对通孔和通孔进行接种和电镀; 对要接合和显影的面板区域的图像曝光的面板施加光致抗蚀剂; 并且在要接合的面板的区域中蚀刻覆盖片和光致抗蚀剂以暴露粘合聚合物。

公开(公告)号：US5442144A

公开(公告)日：1995-08-15

申请号：US298707

申请日：1994-08-31

申请人： William T. Chen ,  Thomas P. Gall ,  James R. Wilcox ,  Tien Y. Wu

发明人： William T. Chen ,  Thomas P. Gall ,  James R. Wilcox ,  Tien Y. Wu

IPC分类号： H05K3/32 ,  H05K3/46 ,  H05K1/00

CPC分类号： H05K3/4632 ,  H05K3/462 ,  H05K2201/0129 ,  H05K2201/015 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K3/328 ,  Y10T29/49126 ,  Y10T29/49165

摘要： A method of making a multilayered circuit board wherein at least two layered subassemblies, each comprising a dielectric layer and at least one conductive layer therein, are bonded together. Each subassembly includes a through-hole extending therethrough which is aligned with a respective through-hole of the other prior to bonding. The subassemblies are compressed at a predetermined pressure (e.g., 300 psi) and then heated to a first temperature (e.g., 300.degree. C.) for an established time period, resulting in formation of a bond between the two through-holes. The resulting alloy formed from this bond possesses a melting point significantly greater than that of the subassembly dielectric (e.g., PTFE). Following this time period, the compressed subassemblies are heated to an even greater temperature (e.g., 380.degree. C.), again for an established time period, to assure dielectric flow. The subassembly is then cooled and the pressure removed. The method possesses two significant features: (1) effective engagement between respective pairs of through-holes in the compressed subassemblies; and (2) prevention of dielectric incursion within the bond formed between the respective pairs of through-holes, which incursion could adversely affect the electrical connection therebetween.

摘要翻译： 一种制造多层电路板的方法，其中至少两个分层的子组件（每个包括电介质层和至少一个导电层）结合在一起。 每个子组件包括贯穿其中的通孔，其在结合之前与相应的通孔对准。 子组件在预定压力（例如，300psi）下被压缩，然后被加热到第一温度（例如，300℃）一段既定的时间段，从而在两个通孔之间形成一个键。 由该键形成的合金具有显着大于组件电介质（例如PTFE）的熔点。 在该时间段之后，将压缩的子组件再次加热到甚至更高的温度（例如380℃），以确定电介质流动。 然后将组件冷却并除去压力。 该方法具有两个重要特征：（1）压缩子组件中各对通孔之间的有效啮合; 和（2）防止在相应的成对的通孔之间形成的接合中的电介质侵入，这种侵入可能不利地影响它们之间的电连接。

公开(公告)号：US5391514A

公开(公告)日：1995-02-21

申请号：US229883

申请日：1994-04-19

申请人： Thomas P. Gall ,  Anthony P. Ingraham

发明人： Thomas P. Gall ,  Anthony P. Ingraham

IPC分类号： H01L21/60 ,  H01L21/28 ,  H01L21/58

CPC分类号： H01L24/81 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/11462 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/81065 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81801 ,  H01L2224/81825 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351

摘要： A method of flip chip bonding an integrated circuit chip to a chip carrier. A high melting temperature composition, such as a binary Pb/Sn alloy, is deposited on contacts on, for example, the chip, and constituents of a low melting composition, such as Bi and Sn, are codeposited on contacts on, for example, the chip carrier. The chip and chip carrier are then heated. This causes the lower melting temperature composition, for example the Bi and Sn, to melt and form a low melting temperature alloy, such as a Bi/Sn alloy. The low melting alloy dissolves the higher melting composition, as Pb/Sn. This results in the formation of a solder bond of a low melting point third composition, such as a ternary alloy of Bi/Pb/Sn.

摘要翻译： 将集成电路芯片倒装芯片连接到芯片载体的方法。 将诸如二元Pb / Sn合金的高熔点组合物沉积在例如芯片上的触点上，并且诸如Bi和Sn的低熔点组合物的成分共沉积在例如， 芯片载体。 然后加热芯片和芯片载体。 这导致较低的熔融温度组合物，例如Bi和Sn熔化并形成诸如Bi / Sn合金的低熔点合金。 低熔点合金溶解较高熔点的组分，如Pb / Sn。 这导致形成低熔点第三组合物如Bi / Pb / Sn的三元合金的焊料接合。