公开(公告)号：US5633516A

公开(公告)日：1997-05-27

申请号：US506193

申请日：1995-07-24

申请人： Tomoyoshi Mishima ,  Katsuhiko Higuchi ,  Mitsuhiro Mori ,  Makoto Kudo ,  Chushiro Kusano

发明人： Tomoyoshi Mishima ,  Katsuhiko Higuchi ,  Mitsuhiro Mori ,  Makoto Kudo ,  Chushiro Kusano

IPC分类号： H01L21/20 ,  H01L21/338 ,  H01L29/205 ,  H01L29/778 ,  H01L29/812 ,  H01S5/223 ,  H01S5/32 ,  H01L31/0328

CPC分类号： H01L29/205 ,  H01L29/7783 ,  H01S5/223 ,  H01S5/3201

摘要： A semiconductor device has a lattice-mismatched crystal structure including a semiconductor film formed on a substrate with an intervening buffer layer. The buffer layer has a plurality of layers, including first sublayers, or regions, in which an element that controls the lattice constant is provided in increasing mole fraction, and second sublayers, or regions, in which the lattice constant is maintained. The first sublayers and second sublayers are provided in alternating fashion. The resulting device has an increased electron mobility as compared with the prior art.

摘要翻译： 半导体器件具有晶格失配的晶体结构，其包括在具有中间缓冲层的衬底上形成的半导体膜。 缓冲层具有包括第一子层或多个区域的多个层，其中控制晶格常数的元素以增加的摩尔分数提供，以及维持晶格常数的第二子层或区域。 以交替方式提供第一子层和第二子层。 所得到的器件与现有技术相比具有增加的电子迁移率。

公开(公告)号：US08742499B2

公开(公告)日：2014-06-03

申请号：US12608751

申请日：2009-10-29

申请人： Shizuki Nakajima ,  Hiroyuki Nagai ,  Yuji Shirai ,  Hirokazu Nakajima ,  Chushiro Kusano ,  Yu Hasegawa ,  Chiko Yorita ,  Yasuo Osone

发明人： Shizuki Nakajima ,  Hiroyuki Nagai ,  Yuji Shirai ,  Hirokazu Nakajima ,  Chushiro Kusano ,  Yu Hasegawa ,  Chiko Yorita ,  Yasuo Osone

IPC分类号： H01L27/082 ,  H01L27/088 ,  H01L21/8222 ,  H01L29/78

CPC分类号： H01L29/7835 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/66 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/16 ,  H01L27/088 ,  H01L29/04 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/41758 ,  H01L29/66659 ,  H01L29/7371 ,  H01L2223/6644 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05171 ,  H01L2224/05553 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10161 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/0206 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/01032 ,  H01L2924/01083 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/013

摘要： In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.

摘要翻译： 在其中形成用于功率放大器模块的功率放大器电路的LDMOSFET元件形成的半导体芯片中，源极突起电极设置在LDMOSFET形成区域中，其中多个源极区域，多个漏极区域和多个栅极 形成用于LDMOSFET元件的电极。 源极突起电极通过源极导体层形成在主要由铝制成的源极焊盘上，该源极导体层比源焊盘厚，主要由铜制成。 在源凸起电极和源极导体层之间不设置树脂膜。

公开(公告)号：US08227836B2

公开(公告)日：2012-07-24

申请号：US12579975

申请日：2009-10-15

申请人： Satoshi Sasaki ,  Yasunari Umemoto ,  Yasuo Osone ,  Tsutomu Kobori ,  Chushiro Kusano ,  Isao Ohbu ,  Kenji Sasaki

发明人： Satoshi Sasaki ,  Yasunari Umemoto ,  Yasuo Osone ,  Tsutomu Kobori ,  Chushiro Kusano ,  Isao Ohbu ,  Kenji Sasaki

IPC分类号： H01L27/082 ,  H01L27/102

CPC分类号： H01L29/7304 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L25/042 ,  H01L27/0605 ,  H01L27/067 ,  H01L28/40 ,  H01L29/0808 ,  H01L29/7371 ,  H01L2223/6627 ,  H01L2223/6644 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19032 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099

摘要： A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.

摘要翻译： 提供了允许半导体器件的热阻降低和小型化的技术。 半导体器件具有多个单位晶体管Q，每个具有单位晶体管Q的第一数量（例如七个）的晶体管形成区域3a，3b和3e以及每个具有第二数量的晶体管形成区域3c和3d（例如， ，四个）单位晶体管Q.晶体管形成区域3c和3d位于晶体管形成区域3a，3b，3e和3f之间，并且第一数量大于第二数量。

公开(公告)号：US07511315B2

公开(公告)日：2009-03-31

申请号：US11108729

申请日：2005-04-19

申请人： Satoru Konishi ,  Tsuneo Endo ,  Hirokazu Nakajima ,  Yasunari Umemoto ,  Satoshi Sasaki ,  Chushiro Kusano ,  Yoshinori Imamura ,  Atsushi Kurokawa

发明人： Satoru Konishi ,  Tsuneo Endo ,  Hirokazu Nakajima ,  Yasunari Umemoto ,  Satoshi Sasaki ,  Chushiro Kusano ,  Yoshinori Imamura ,  Atsushi Kurokawa

IPC分类号： H01L21/00 ,  H01L29/34 ,  H01L23/48 ,  H01L21/4763

CPC分类号： H01L29/4933 ,  H01L21/84 ,  H01L23/4824 ,  H01L23/49844 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/16 ,  H01L29/456 ,  H01L29/7835 ,  H01L2224/1403 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.

摘要翻译： 半导体器件具有在布线基板的下表面上形成的用于GND的外部布线。 连接到GND的外部配线的多个通孔形成为穿透布线基板。 包括HBT的高功率的第一半导体芯片安装在布线基板的主表面上。 第一半导体芯片的发射极电极与形成在第一半导体芯片中的多个HBT的发射极共同连接。 发射极电极沿HBT排列的方向延伸。 第一半导体芯片安装在布线基板上，使得多个通孔与发射极电极连接。 散热值比第一半导体芯片低的第二半导体芯片安装在第一半导体芯片上。

公开(公告)号：US4331506A

公开(公告)日：1982-05-25

申请号：US212213

申请日：1980-12-02

申请人： Akira Sasano ,  Toshio Nakano ,  Ken Tsutsui ,  Chushiro Kusano ,  Tadaaki Hirai ,  Eiichi Maruyama

发明人： Akira Sasano ,  Toshio Nakano ,  Ken Tsutsui ,  Chushiro Kusano ,  Tadaaki Hirai ,  Eiichi Maruyama

IPC分类号： H01J9/233 ,  H01J31/46 ,  H01J31/26

CPC分类号： H01J31/46 ,  H01J9/233

摘要： A method of manufacturing a target of an image pickup tube comprising the steps of: forming a plurality of groups of transparent conductive signal electrodes on a transparent insulating base plate; forming a first layer on at least a portion constituting an image area of the image pickup tube, said first layer being substantially insoluble in etching liquid used for etching an insulating layer to constitute an intermediate layer insulator in a double layered interconnection structure; forming, after formation of said first layer, an insulating layer to constitute said intermediate-layer insulator; removing a predetermined portion of said insulating layer, removing said first layer together with said insulating layer located thereon; forming bus bars; and forming a photoconductive layer on said plurality of groups of the transparent conductive signal electrodes.This invention provides an excellent method for mass production.

摘要翻译： 一种制造图像拾取管的目标的方法，包括以下步骤：在透明绝缘基板上形成多组透明导电信号电极; 在构成图像拾取管的图像区域的至少一部分上形成第一层，所述第一层基本上不溶于用于蚀刻绝缘层的蚀刻液，以构成双层互连结构中的中间层绝缘体; 在形成所述第一层之后形成构成所述中间层绝缘体的绝缘层; 去除所述绝缘层的预定部分，与位于其上的所述绝缘层一起去除所述第一层; 形成母线; 以及在所述多个透明导电信号电极组上形成光电导层。 本发明提供了一种很好的批量生产方法。

公开(公告)号：US20070164316A1

公开(公告)日：2007-07-19

申请号：US11723769

申请日：2007-03-22

申请人： Isao Ohbu ,  Chushiro Kusano ,  Yasunari Umemoto ,  Atsushi Kurokawa

发明人： Isao Ohbu ,  Chushiro Kusano ,  Yasunari Umemoto ,  Atsushi Kurokawa

IPC分类号： H01L31/00

CPC分类号： H01L29/7304 ,  H01L27/0605 ,  H01L29/7371 ,  H03F2200/444 ,  H03F2203/21178

摘要： A heterojunction bipolar transistor with InGaP as the emitter layer and capable of both reliable electrical conduction and thermal stability wherein a GaAs layer is inserted between the InGaP emitter layer and AlGaAs ballast resistance layer, to prevent holes reverse-injected from the base layer from diffusing and reaching the AlGaAs ballast resistance layer.

公开(公告)号：US20060138460A1

公开(公告)日：2006-06-29

申请号：US11319084

申请日：2005-12-28

申请人： Satoshi Sasaki ,  Yasunari Umemoto ,  Yasuo Osone ,  Tsutomu Kobori ,  Chushiro Kusano ,  Isao Ohbu ,  Kenji Sasaki

发明人： Satoshi Sasaki ,  Yasunari Umemoto ,  Yasuo Osone ,  Tsutomu Kobori ,  Chushiro Kusano ,  Isao Ohbu ,  Kenji Sasaki

IPC分类号： H01L31/109

CPC分类号： H01L29/7304 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L25/042 ,  H01L27/0605 ,  H01L27/067 ,  H01L28/40 ,  H01L29/0808 ,  H01L29/7371 ,  H01L2223/6627 ,  H01L2223/6644 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19032 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099

摘要： A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f and the first number is larger than the second number.

摘要翻译： 提供了允许半导体器件的热阻降低和小型化的技术。 半导体器件具有多个单位晶体管Q，具有第一数量（7）的单位晶体管Q的晶体管形成区域3a，3b和3e，以及分别具有第二 （4个）晶体管Q.晶体管形成区域3c和3d位于晶体管形成区域3a，3b，3e和3f之间，第一个数量大于第二个数量。

公开(公告)号：US07045877B2

公开(公告)日：2006-05-16

申请号：US10420740

申请日：2003-04-23

申请人： Yasunari Umemoto ,  Hideyuki Ono ,  Tomonori Tanoue ,  Yasuo Ohsone ,  Isao Ohbu ,  Chushiro Kusano ,  Atsushi Kurokawa ,  Masao Yamane

发明人： Yasunari Umemoto ,  Hideyuki Ono ,  Tomonori Tanoue ,  Yasuo Ohsone ,  Isao Ohbu ,  Chushiro Kusano ,  Atsushi Kurokawa ,  Masao Yamane

IPC分类号： H01L31/072

CPC分类号： H01L27/0825 ,  H01L27/0259 ,  H01L29/7371 ,  H01L2224/48091 ,  H01L2224/73265 ,  H03K17/08146 ,  H03K17/615 ,  H01L2924/00014

摘要： The invention is directed to improve resistance to destruction of a semiconductor device. A protection circuit having a plurality of bipolar transistors which are Darlington connected between outputs (collector and emitter) of an amplification circuit of a high output is electrically connected in parallel with the amplification circuit. The amplification circuit has a plurality of unit HBTs (Heterojunction Bipolar Transistors) which are connected in parallel with each other. The protection circuit has a two-stage configuration including a first group of a protection circuit having a plurality of bipolar transistors Q1 to Q5 and a second group of a protection circuit having a plurality of bipolar transistors.

摘要翻译： 本发明旨在提高对半导体器件的破坏性。 具有连接在高输出的放大电路的输出（集电极和发射极）之间的达林顿的多个双极晶体管的保护电路与放大电路并联电连接。 放大电路具有彼此并联连接的多个单元HBT（异质结双极晶体管）。 保护电路具有包括具有多个双极型晶体管Q 1至Q 5的第一组保护电路和具有多个双极晶体管的第二组保护电路的两级配置。

公开(公告)号：US5514992A

公开(公告)日：1996-05-07

申请号：US273800

申请日：1994-07-12

申请人： Satoshi Tanaka ,  Akishige Nakajima ,  Eiichi Hase ,  Chushiro Kusano

发明人： Satoshi Tanaka ,  Akishige Nakajima ,  Eiichi Hase ,  Chushiro Kusano

IPC分类号： H03D7/12 ,  H01L27/095 ,  H03F1/08 ,  H03F1/22 ,  H03B19/00 ,  H03K3/353

CPC分类号： H03F1/226 ,  H01L27/095

摘要： An electronic circuit is provided with a first field effect transistor and a second field effect transistor, in which a drain of the first field effect transistor connected to a source of the second field effect transistor. This electronic circuit inputs a first signal to a gate electrode of the first field effect transistor, inputs a second signal to a gate electrode of the second field effect transistor and outputs a signal from a drain of the second field effect transistor. This electronic circuit is a cascode circuit related to the current drivability of the second field effect transistor is set to be larger than the current drivability of the first field effect transistor, and there is an effect that third-order or higher order distortion characteristics of a cascode type or dual-gate circuit can be reduced.

摘要翻译： 电子电路设置有第一场效应晶体管和第二场效应晶体管，其中第一场效应晶体管的漏极连接到第二场效应晶体管的源极。 该电子电路将第一信号输入到第一场效应晶体管的栅电极，将第二信号输入到第二场效应晶体管的栅极，并输出来自第二场效应晶体管的漏极的信号。 该电子电路是与第二场效应晶体管的电流驱动能力相关的共源共栅电路被设定为大于第一场效应晶体管的电流驱动能力，并且具有以下效果：第一场效应晶体管的三阶或更高阶失真特性 可以降低共源共栅型或双栅极电路。

公开(公告)号：US08860093B2

公开(公告)日：2014-10-14

申请号：US13538121

申请日：2012-06-29

申请人： Satoshi Sasaki ,  Yasunari Umemoto ,  Yasuo Osone ,  Tsutomu Kobori ,  Chushiro Kusano ,  Isao Ohbu ,  Kenji Sasaki

发明人： Satoshi Sasaki ,  Yasunari Umemoto ,  Yasuo Osone ,  Tsutomu Kobori ,  Chushiro Kusano ,  Isao Ohbu ,  Kenji Sasaki

IPC分类号： H01L27/102 ,  H01L29/737 ,  H03F3/195 ,  H01L23/66 ,  H01L27/06 ,  H01L23/00

CPC分类号： H01L29/7304 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L25/042 ,  H01L27/0605 ,  H01L27/067 ,  H01L28/40 ,  H01L29/0808 ,  H01L29/7371 ,  H01L2223/6627 ,  H01L2223/6644 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19032 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099

摘要： A technology which allows a reduction in the thermal resistance of a semiconductor device used in a radio communication device, and the miniaturization thereof is provided. For example, the semiconductor device can include a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.

摘要翻译： 提供了允许降低无线电通信装置中使用的半导体装置的热阻的技术及其小型化。 例如，半导体器件可以包括多个单位晶体管Q，具有单位晶体管Q的第一数量（例如7个）的晶体管形成区域3a，3b和3e以及每个具有单位晶体管Q的晶体管形成区域3c和3d 晶体管形成区域3c和3d位于晶体管形成区域3a，3b，3e和3f之间，第一数量大于第二数量。