Connecting through vias to devices
    2.
    发明授权
    Connecting through vias to devices 有权
    通过通孔连接到设备

    公开(公告)号:US08624324B1

    公开(公告)日:2014-01-07

    申请号:US13572337

    申请日:2012-08-10

    IPC分类号: H01L29/423 H01L21/28

    摘要: Methods and devices for connecting a through via and a terminal of a transistor formed of a strained silicon material are provided. The terminal, which can be a source or a drain of a NMOS or a PMOS transistor, is formed within a substrate. A first contact within a first inter-layer dielectric (ILD) layer over the substrate is formed over and connected to the terminal. A through via extends through the first ILD layer into the substrate. A second contact is formed over and connected to the first contact and the through via within a second ILD layer and a contact etch stop layer (CESL). The second ILD layer is over the CESL, and the CESL is over the first ILD layer, which are all below a first inter-metal dielectric (IMD) layer and the first metal layer of the transistor.

    摘要翻译: 提供了用于连接由应变硅材料形成的晶体管的通孔和端子的方法和装置。 作为NMOS或PMOS晶体管的源极或漏极的端子形成在衬底内。 在衬底上的第一层间电介质(ILD)层内的第一接触形成在端子上并连接到端子。 通孔延伸穿过第一ILD层进入衬底。 在第二ILD层和接触蚀刻停止层(CESL)内形成第二触点并连接到第一触点和穿通通孔。 第二ILD层在CESL之上,并且CESL在第一ILD层之上,它们都在第一金属间电介质(IMD)层和晶体管的第一金属层的下面。

    Planar coil and method of making the same
    5.
    发明授权
    Planar coil and method of making the same 失效
    平面线圈及其制作方法

    公开(公告)号:US08310328B2

    公开(公告)日:2012-11-13

    申请号:US12899836

    申请日:2010-10-07

    IPC分类号: H01F5/00 H01F27/28 H01L27/08

    摘要: A method of making a planar coil is disclosed in the present invention. First, a substrate having a trench is provided. Then, a barrier and a seed layer are formed on the substrate in sequence. An isolative layer is used for guiding a conductive material to flow into a lower portion of the trench such that accumulation of the conductive material at opening of the trench is prevented before the lower portion of the trench is completely filled up, thereby avoiding gap formation in the trench.

    摘要翻译: 在本发明中公开了制造平面线圈的方法。 首先,提供具有沟槽的衬底。 然后,依次在基板上形成阻挡层和种子层。 隔离层用于引导导电材料流入沟槽的下部,使得沟槽开口处的导电材料的积聚在沟槽的下部被完全填充之前被阻止,从而避免了在沟槽中的间隙形成 沟渠。

    Method of forming circuit patterns on semiconductor wafers using two optical steppers having nonaligned imaging systems
    10.
    发明授权
    Method of forming circuit patterns on semiconductor wafers using two optical steppers having nonaligned imaging systems 有权
    使用具有非对准成像系统的两个光学步进器在半导体晶片上形成电路图案的方法

    公开(公告)号:US06340547B1

    公开(公告)日:2002-01-22

    申请号:US09481032

    申请日:2000-01-11

    IPC分类号: G03F900

    摘要: A method of forming circuit patterns on a semiconductor wafer using two different image steppers having nonaligned optical image systems achieves optical alignment of multiple overlays with high accuracy. A first alignment mark is imaged by the first stepper onto a material layer deposited on the wafer, and a second alignment mark is imaged onto a subsequently deposited material layer using the second stepper. Alignment of the two marks, and thus of successively imaged, overlying circuit patterns, is achieved by translating the optical coordinates of the second alignment system into the those of the first alignment system, and then making corresponding two dimensional adjustment of the wafer position relative to the second stepper.

    摘要翻译: 使用具有非对准光学图像系统的两个不同的图像步进器在半导体晶片上形成电路图案的方法实现了高精度的多个覆盖层的光学对准。 将第一对准标记由第一步进器成像到沉积在晶片上的材料层上,并且使用第二步进器将第二对准标记成像到随后沉积的材料层上。 通过将第二对准系统的光学坐标转换为第一对准系统的光学坐标,然后相对于第二对准系统的晶片位置进行相应的二维调整来实现两个标记的对准,并且因此连续成像的上覆电路图案的对准 第二步。