公开(公告)号：US20170317001A1

公开(公告)日：2017-11-02

申请号：US15646189

申请日：2017-07-11

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Klaus Schiess ,  Oliver Haeberlen ,  Matteo-Alessandro Kutschak

IPC: H01L23/31 ,  H01L23/14 ,  H01L23/495 ,  H01L25/10 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: A device includes a driver circuit, a first semiconductor chip monolithically integrated with the driver circuit in a first semiconductor material, and a second semiconductor chip integrated in a second semiconductor material. The second semiconductor material is a compound semiconductor.

公开(公告)号：US09735078B2

公开(公告)日：2017-08-15

申请号：US14254139

申请日：2014-04-16

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Klaus Schiess ,  Oliver Haeberlen ,  Matteo-Alessandro Kutschak

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L23/3157 ,  H01L21/4842 ,  H01L21/568 ,  H01L23/142 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/48 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/06181 ,  H01L2224/24175 ,  H01L2224/24246 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/40137 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/73263 ,  H01L2224/73267 ,  H01L2224/8382 ,  H01L2224/92244 ,  H01L2225/1029 ,  H01L2225/1047 ,  H01L2924/00 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/014

Abstract: A device includes a first semiconductor chip that is arranged over a first carrier and includes a first electrical contact. The device further includes a second semiconductor chip arranged over a second carrier and including a second electrical contact arranged over a surface of the second semiconductor chip facing the second carrier. The second carrier is electrically coupled to the first electrical contact and the second electrical contact.

公开(公告)号：US09412626B2

公开(公告)日：2016-08-09

申请号：US14935510

申请日：2015-11-09

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess ,  Bernd Roemer ,  Edward Fuergut

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/34 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L23/552

CPC classification number: H01L21/565 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/495 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/552 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099

Abstract: A method for manufacturing a chip arrangement, including disposing a chip over a carrier, wherein the bottom side of the chip is electrically connected to the first carrier side via one or more contact pads on the chip bottom side, disposing a first encapsulation material over the first carrier side, wherein the first encapsulation material at least partially surrounds the chip, and disposing a second encapsulation material over a second carrier side, wherein the second encapsulation material is in direct contact with the second carrier side.

Abstract translation: 一种用于制造芯片布置的方法，包括在载体上布置芯片，其中芯片的底侧通过芯片底侧上的一个或多个接触焊盘电连接到第一载体侧，在第一封装材料上设置第一封装材料 第一载体侧，其中第一封装材料至少部分地围绕芯片，并且在第二载体侧上设置第二封装材料，其中第二封装材料与第二载体侧直接接触。

公开(公告)号：US20150303128A1

公开(公告)日：2015-10-22

申请号：US14254139

申请日：2014-04-16

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Klaus Schiess ,  Oliver Haeberlen ,  Matteo-Alessandro Kutschak

IPC: H01L23/373 ,  H01L23/522 ,  H01L23/31 ,  H01L25/10 ,  H01L23/495

CPC classification number: H01L23/3157 ,  H01L21/4842 ,  H01L21/568 ,  H01L23/142 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/48 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/06181 ,  H01L2224/24175 ,  H01L2224/24246 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/40137 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/73263 ,  H01L2224/73267 ,  H01L2224/8382 ,  H01L2224/92244 ,  H01L2225/1029 ,  H01L2225/1047 ,  H01L2924/00 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/014

Abstract: A device includes a first semiconductor chip that is arranged over a first carrier and includes a first electrical contact. The device further includes a second semiconductor chip arranged over a second carrier and including a second electrical contact arranged over a surface of the second semiconductor chip facing the second carrier. The second carrier is electrically coupled to the first electrical contact and the second electrical contact.

Abstract translation: 一种器件包括布置在第一载体上并包括第一电触点的第一半导体芯片。 该装置还包括布置在第二载体上的第二半导体芯片，并且包括布置在面向第二载体的第二半导体芯片的表面上的第二电触点。 第二载体电耦合到第一电接触和第二电接触。

公开(公告)号：US20140151856A1

公开(公告)日：2014-06-05

申请号：US13693205

申请日：2012-12-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess

IPC: H01L23/34 ,  H01L21/56

CPC classification number: H01L23/34 ,  H01L21/56 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/49827 ,  H01L23/5389 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The chip module includes a carrier, a semiconductor chip arranged on or embedded inside the carrier, and an insulation layer that at least partly covers a face of the carrier. The dielectric constant ∈r and the thermal conductivity λ of the insulation layer satisfy the condition λ·∈r

Abstract translation: 芯片模块包括载体，布置在载体上或嵌入载体内部的半导体芯片，以及至少部分覆盖载体的表面的绝缘层。 绝缘层的介电常数εr和热导率λ满足条件λ·∈r<4.0 W·m-1·K-1。

公开(公告)号：US20130328213A1

公开(公告)日：2013-12-12

申请号：US13965630

申请日：2013-08-13

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Henrik Ewe ,  Klaus Schiess ,  Manfred Mengel

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/481 ,  H01L21/50 ,  H01L23/36 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/25 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82102 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

Abstract: One aspect is a device including a carrier comprising a first conducting layer, a first insulating layer over the first conducting layer, and at least one first through-connection from a first face of the first insulating layer to a second face of the first insulating layer. A semiconductor chip is attached to the carrier and a second insulating layer is over the carrier and the semiconductor chip. A metal layer is over the second insulating layer. A second through-connection is through the second insulating layer electrically coupling the semiconductor chip to the metal layer. A third through-connection is through the second insulating layer electrically coupling the carrier to the metal layer.

Abstract translation: 一个方面是包括载体的器件，其包括第一导电层，在第一导电层上的第一绝缘层，以及从第一绝缘层的第一面到第一绝缘层的第二面的至少一个第一通孔连接 。 半导体芯片附着到载体上，第二绝缘层位于载体和半导体芯片之上。 金属层在第二绝缘层之上。 第二直通连接通过第二绝缘层将半导体芯片电耦合到金属层。 第三直通连接是通过第二绝缘层将载体电耦合到金属层。

公开(公告)号：US11676881B2

公开(公告)日：2023-06-13

申请号：US16929223

申请日：2020-07-15

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Teck Sim Lee ,  Klaus Schiess ,  Xaver Schloegel ,  Lee Shuang Wang ,  Mohd Hasrul Zulkifli

IPC: H01L23/367 ,  H01L23/12 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/3677 ,  H01L21/4871 ,  H01L23/12 ,  H01L23/3107

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a chip carrier, a semiconductor chip attached to the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package. A second side of the semiconductor package opposite the first side is configured to be surface mounted to an application board.

公开(公告)号：US10763246B2

公开(公告)日：2020-09-01

申请号：US15646189

申请日：2017-07-11

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Klaus Schiess ,  Oliver Haeberlen ,  Matteo-Alessandro Kutschak

IPC: H01L23/495 ,  H01L25/11 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/14 ,  H01L21/48 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L27/088 ,  H01L21/56

Abstract: A device includes a driver circuit, a first semiconductor chip monolithically integrated with the driver circuit in a first semiconductor material, and a second semiconductor chip integrated in a second semiconductor material. The second semiconductor material is a compound semiconductor.

公开(公告)号：US09595487B2

公开(公告)日：2017-03-14

申请号：US13925900

申请日：2013-06-25

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Klaus Schiess ,  Anton Mauder

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/40 ,  H01L23/495 ,  H05K1/02 ,  H05K3/34

CPC classification number: H01L23/3675 ,  H01L23/3107 ,  H01L23/4006 ,  H01L23/4093 ,  H01L23/49562 ,  H01L2224/06181 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1431 ,  H05K1/0203 ,  H05K1/0265 ,  H05K1/0287 ,  H05K3/3447 ,  H05K2201/066 ,  H05K2201/09227 ,  H01L2924/00

Abstract: Various embodiments may provide a circuit arrangement. The circuit arrangement may include a carrier having at least one electrically conductive line; a plurality of discrete encapsulated integrated circuits arranged on the carrier; wherein a first integrated circuit of the plurality of integrated circuits is in electrical contact with a second integrated circuit of the plurality of integrated circuits to form a first current path bypassing the carrier; and wherein the first integrated circuit of the plurality of integrated circuits is in electrical contact with the second integrated circuit of the plurality of integrated circuits to form a second current path via the at least one electrically conductive line.

Abstract translation: 各种实施例可以提供电路装置。 电路装置可以包括具有至少一个导电线的载体; 布置在载体上的多个分立封装集成电路; 其中所述多个集成电路的第一集成电路与所述多个集成电路中的第二集成电路电接触以形成绕过所述载体的第一电流路径; 并且其中所述多个集成电路中的所述第一集成电路与所述多个集成电路中的所述第二集成电路电接触以形成经由所述至少一个导电线路的第二电流路径。

公开(公告)号：US09449902B2

公开(公告)日：2016-09-20

申请号：US14535138

申请日：2014-11-06

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess

IPC: H01L29/76 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L29/2003 ,  H01L29/78 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2224/85801 ,  H01L2224/8585 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00012

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads.

Abstract translation: 根据本发明的实施例，半导体封装包括具有第一管芯焊盘的第一引线框架和具有第二管芯焊盘和多个引线的第二引线框架。 第二模板设置在第一模板上。 半导体芯片设置在第二裸片上。 半导体芯片在面向第二引线框架的第一面上具有多个接触区域。 多个接触区域耦合到多个引线。