公开(公告)号：US09583671B2

公开(公告)日：2017-02-28

申请号：US14629487

申请日：2015-02-23

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Ilyas Mohammed ,  Masud Beroz

IPC: H01L21/00 ,  H01L33/00 ,  H01L33/06 ,  H01L31/0352 ,  H01L31/105 ,  B82Y20/00 ,  H01L33/32 ,  H01L33/62 ,  H01L29/06 ,  H01L31/00 ,  H01L33/24 ,  H01S5/20 ,  H01S5/34 ,  H01S5/343 ,  H01S5/32

CPC classification number: H01L33/0075 ,  B82Y20/00 ,  H01L31/035236 ,  H01L31/105 ,  H01L33/0025 ,  H01L33/0066 ,  H01L33/06 ,  H01L33/24 ,  H01L33/32 ,  H01L33/62 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01S5/2009 ,  H01S5/3205 ,  H01S5/3407 ,  H01S5/34333

Abstract: Improved quantum efficiency of multiple quantum wells. In accordance with an embodiment of the present invention, an article of manufacture includes a p side for supplying holes and an n side for supplying electrons. The article of manufacture also includes a plurality of quantum well periods between the p side and the n side, each of the quantum well periods includes a quantum well layer and a barrier layer, with each of the barrier layers having a barrier height. The plurality of quantum well periods include different barrier heights.

Abstract translation: 提高多量子阱的量子效率。 根据本发明的实施例，制品包括用于供应空穴的p侧和用于提供电子的n侧。 制品还包括在p侧和n侧之间的多个量子阱周期，每个量子阱周期包括量子阱层和阻挡层，其中每个势垒层具有势垒高度。 多个量子阱周期包括不同的屏障高度。

公开(公告)号：US09570385B2

公开(公告)日：2017-02-14

申请号：US14602984

申请日：2015-01-22

Applicant: Invensas Corporation

Inventor： Bong-Sub Lee ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Liang Wang ,  Laura Wills Mirkarimi ,  Arkalgud R. Sitaram

IPC: H05K3/02 ,  H05K3/10 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/16 ,  H05K3/18

CPC classification number: H05K1/097 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/113 ,  H05K1/165 ,  H05K3/188 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/5313 ,  H01L2924/00

Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.

Abstract translation: 内插器电路（130）由可能牺牲的基板（210）形成，所述牺牲基板（210）从由导电涂层（130“）覆盖的多孔芯（130'）形成，所述导电涂层增加导电性。 核心由纳米颗粒油墨印刷。 然后形成支撑件（120S），例如 通过模制，以机械地稳定电路。 在形成电路或支撑件的同时，可以使用磁场来稳定电路。 还提供其他功能。

公开(公告)号：US20170018529A1

公开(公告)日：2017-01-19

申请号：US15208985

申请日：2016-07-13

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Reynaldo Co ,  Scott McGrath ,  Ashok S. Prabhu ,  Sangil Lee ,  Liang Wang ,  Hong Shen

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/02335 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/9222 ,  H01L2225/06506 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1037 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2224/19

Abstract: A microelectronic assembly includes a stack of semiconductor chips each having a front surface defining a respective plane of a plurality of planes. A chip terminal may extend from a contact at a front surface of each chip in a direction towards the edge surface of the respective chip. The chip stack is mounted to substrate at an angle such that edge surfaces of the chips face a major surface of the substrate that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. An electrically conductive material electrically connects the chip terminals with corresponding substrate contacts.

Abstract translation: 微电子组件包括堆叠的半导体芯片，每个半导体芯片具有限定多个平面的相应平面的前表面。 芯片端子可以沿着朝向相应芯片的边缘表​​面的方向从每个芯片的前表面处的触点延伸。 芯片堆叠以一定角度安装到基板，使得芯片的边缘表​​面面向基板的主表面，该主表面限定横向于即不平行于多个平行平面的第二平面。 导电材料将芯片端子与相应的衬底触点电连接。

公开(公告)号：US09496154B2

公开(公告)日：2016-11-15

申请号：US14488187

申请日：2014-09-16

Applicant: Invensas Corporation

Inventor： Eric S. Tosaya ,  Rajesh Katkar ,  Liang Wang ,  Cyprian Emeka Uzoh

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/563 ,  H01L21/481 ,  H01L23/13 ,  H01L23/3178 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/06102 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/16237 ,  H01L2224/2908 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29388 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81395 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83385 ,  H01L2224/83856 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83

Abstract: A microelectronic component (110, 120) has a contact pad (110C, 120C, 920C) recessed in a cavity (410) and covered by underfill tape (130). The cavity has a void (410V) below the underfill tape. A protruding contact pad of another microelectronic component ruptures the underfill tape to enter the cavity and bond to the recessed contact pad. The void helps in rupturing the underfill tape, thus reducing the amount of underfill residue between the two contact pads and improving the contact resistance. Also provided is a microelectronic component having a substrate with a cavity and having a through-substrate via extending into the cavity. Other features are also provided.

Abstract translation: 微电子部件（110,120）具有凹陷在空腔（410）中并被底部填充带（130）覆盖的接触垫（110C，120C，920C）。 空腔在底部填充带下方具有空隙（410V）。 另一微电子元件的突出的接触垫破坏了底部填充带进入腔并结合到凹陷接触垫。 该空隙有助于破裂底部填充带，从而减少两个接触垫之间的底部填充残余物的量并改善接触电阻。 还提供了一种微电子部件，其具有带有空腔的基板，并且具有延伸到空腔中的贯穿基板。 还提供其他功能。

公开(公告)号：US20160315047A1

公开(公告)日：2016-10-27

申请号：US15200554

申请日：2016-07-01

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Hong Shen ,  Zhuowen Sun ,  Liang Wang ,  Guilian Gao

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Abstract translation: 在具有穿过衬底（104）并且突出在衬底上方的导电通路（114）的微电子部件中，导电特征（120E.A，120E.B）设置在衬底上方，该衬底环绕导电通孔突起（114'） ）以形成电容器，电磁屏蔽以及可能的其他元件。 还提供了其它特征和实施例。

公开(公告)号：US09437536B1

公开(公告)日：2016-09-06

申请号：US14885466

申请日：2015-10-16

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Rajesh Katkar ,  Hong Shen ,  Cyprian Emeka Uzoh ,  Belgacem Haba

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/498 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2924/1427 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19102 ,  H01L2224/81

Abstract: A method of making an assembly can include forming a circuit structure defining front and rear surfaces, and forming a substrate onto the rear surface. The forming of the circuit structure can include forming a first dielectric layer coupled to the carrier. The first dielectric layer can include front contacts configured for joining with contacts of one or more microelectronic elements, and first traces. The forming of the circuit structure can include forming rear conductive elements at the rear surface coupled with the front contacts through the first traces. The forming of the substrate can include forming a dielectric element directly on the rear surface. The dielectric element can have first conductive elements facing the rear conductive elements and joined thereto. The dielectric element can include second traces coupled with the first conductive elements. The forming of the substrate can include forming terminals at a surface of the substrate.

Abstract translation: 制造组件的方法可以包括形成限定前表面和后表面的电路结构，以及在后表面上形成衬底。 电路结构的形成可以包括形成耦合到载体的第一介电层。 第一电介质层可以包括构造成与一个或多个微电子元件的触点和第一迹线接合的前触点。 电路结构的形成可以包括通过第一迹线在与前触点耦合的后表面处形成后导电元件。 基板的形成可以包括直接在后表面上形成电介质元件。 电介质元件可以具有面向后导电元件并与其连接的第一导电元件。 电介质元件可以包括与第一导电元件耦合的第二迹线。 基板的形成可以包括在基板的表面上形成端子。

公开(公告)号：US09397038B1

公开(公告)日：2016-07-19

申请号：US14633746

申请日：2015-02-27

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Hong Shen ,  Zhuowen Sun ,  Liang Wang ,  Guilian Gao

IPC: H01L21/44 ,  H01L23/04 ,  H01L23/52 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

Abstract translation: 在具有穿过衬底（104）并且突出在衬底上方的导电通路（114）的微电子部件中，导电特征（120E.A，120E.B）设置在衬底上方，该衬底环绕导电通孔突起（114'） ）以形成电容器，电磁屏蔽以及可能的其他元件。 还提供了其它特征和实施例。

公开(公告)号：US20150318344A1

公开(公告)日：2015-11-05

申请号：US14268899

申请日：2014-05-02

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Hong Shen ,  Rajesh Katkar

IPC: H01L49/02 ,  H01L23/00

CPC classification number: H01L28/60 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L25/11 ,  H01L25/115 ,  H01L25/165 ,  H01L25/50 ,  H01L28/40 ,  H01L28/65 ,  H01L2224/05009 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1205 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/00

Abstract: A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

Abstract translation: 制造集成电路封装的方法包括提供具有限定空腔的第一区域的处理晶片。 在第一区域形成电容器。 电容器具有一对电极，每对电极耦合到一对导电焊盘中的一个，其至少一个设置在处理晶片的下表面上。 还提供了具有上表面的插入件，其具有导电焊盘和设置在其上的至少一个半导体管芯。 芯片具有与内插器的再分配层（RDL）电导耦合的集成电路。 把手晶片的下表面被结合到插入件的上表面，使得模具设置在空腔的下方或内部，并且处理晶片的导电焊盘以金属间隔结合到插入件的导电焊盘上， 金属键。

公开(公告)号：US09117827B1

公开(公告)日：2015-08-25

申请号：US14268899

申请日：2014-05-02

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Hong Shen ,  Rajesh Katkar

IPC: H01L21/00 ,  H01L21/56

Abstract: A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

公开(公告)号：US20150041208A1

公开(公告)日：2015-02-12

申请号：US13961217

申请日：2013-08-07

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Ilyas Mohammed ,  Belgacem Haba

IPC: H05K3/42 ,  H05K1/11 ,  H05K1/02 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K3/42 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/16225 ,  H05K1/0296 ,  H05K1/11 ,  Y10T29/49204

Abstract: Components and methods of making the same are disclosed herein. In one embodiment, a method of forming a component comprises forming metal anchoring elements at a first surface of a support element having first and second oppositely facing surfaces, the support element having a thickness extending in a first direction between the first and second surfaces, wherein each anchoring element has a downwardly facing overhang surface; and then forming posts having first ends proximate the first surface and second ends disposed above the respective first ends and above the first surface, wherein a laterally extending portion of each post contacts at least a first area of the overhang surface of the respective anchoring element and extends downwardly therefrom, and the overhang surface of the anchoring element resists axial and shear forces applied to the posts at positions above the anchoring elements.

Abstract translation: 组合物及其制备方法在本文中公开。 在一个实施例中，形成部件的方法包括在具有第一和第二相对面对的表面的支撑元件的第一表面处形成金属锚定元件，所述支撑元件具有在第一和第二表面之间沿第一方向延伸的厚度，其中 每个锚固元件具有面向下的突出表面; 然后形成具有靠近第一表面的第一端的柱和设置在相应的第一端上方并在第一表面之上的第二端，其中每个柱的横向延伸部分接触相应锚固元件的伸出表面的至少第一区域，以及 从其向下延伸，并且锚固元件的伸出表面抵抗在锚固元件上方的位置处施加到柱的轴向和剪切力。